View SAA7803_2272781.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the SAA7803 has the same features and pinning as the saa7804 and saa7806 devices. the SAA7803 is a multi chip module containing two additional memories, ?ash and sram, to support code development. this ic is intended for development use only and may therefore not comply with all aspects of the philips semiconductors general quality speci?cation for integrated circuits (snw-fq-611). this ic can therefore also not be the subject of any existing or future quality agreement. all warranties are hereby disclaimed and philips accepts no liability or indemnity whatsoever as to the use of this ic. this ic contains multiple memories along side the audio device resulting in higher levels of emitted noise which may fail fcc certi?cation in some application. for production the saa7804 or saa7806 must be used. 2. features 2.1 hardware features n channel decoder based on saa7817 ic design n digital servo based on saa7824 ic design n 32-bit embedded arm7 risc microprocessor supporting both 32-bit and 16-bit thumb ? instruction sets n mask programmed internal program rom for microprocessor n additional memory for code development n register structure redesigned to utilize the complete 32-bit bandwidth of the integrated microprocessor bus architecture n programmable clock frequency for arm ? microprocessor - allowing users to trade-off power consumption and processing power depending on requirements n microprocessor access to digital representations of the diode input signals from the optical pick up; the microprocessor can also generate the servo output signals ra, fo, sl and allows the possibility of additional servo algorithms or a complete servo implementation in software n microprocessor access to audio streams; both from the internal cd decoder and an external stereo auxiliary input (e.g. an analog source from a tuner; converted to digital via on-chip adcs) to allow audio processing algorithms in the arm microprocessor; e.g. bass boost and volume control n two general purpose analog inputs (a_in_1 and a_in_2) allowing the arm microprocessor access to other external analog signals; e.g. low cost keypad; temperature sensor; via on-chip adcs n two analog inputs for external audio sources (e.g. tuner) which can be accessed by the arm for audio processing SAA7803 one chip cd audio device rev. 01 19 april 2005 objective data sheet 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 2 of 74 philips semiconductors SAA7803 one chip cd audio device n slave i 2 s-bus mode in which the channel decoder can synchronize the cd playback speed to an input i 2 s-bus clock n integrated digital hf/mirror detector with measurement of minimum and maximum peak values, amplitude and offset n integrated lcd controller/driver (pins multiplexed with general purpose input/outputs (gpios) n integrated cd-text decoder n 1 , 2 , 4 or 6 decode speed, clv or cav modes n qfp100 package with 0.65 mm pin pitch n separate left and right channel digital silence detect available on kill pins n digital silence detection available on loopback data from external source as well as internal data n filterless pseudo-bitstream audio dac; thd = - 80 db and s/n = 90 db; with minimal external components n separate line and headphone outputs for audio dac n selectable quiescent current for headphone buffers - allows users to choose between low-power consumption or lower distortion performance n loop back mode allowing the use of integrated dac with external i 2 s-bus/eiaj sources n compatible with voltage mode mechanisms n on-chip buffering and ?ltering of the diode signals from the mechanism in order to optimize the signals for the decoder and servo parts n lf (servo) signals converted to digital representations by sigma delta adcs shared between pairs of channels to minimize dc offset between channels n hf part summed from signals d1 to d4 and converted to digital signals by hf 6-bit adc n digitally controlled selectable dc offset cancellation of quiescent mechanism voltages and dark currents; additional ?ne dc offset cancellation in digital domain n eye pattern monitor system to observe selectable points within the analog preampli?er n current and average jitter values available via registers n on-chip laser power control; up to maximum currents of 120 ma n laser on-off control; including soft start control - zero to nominal output power in 1 ms n monitor control and feedback circuit to maintain nominal output power throughout the life of laser n con?gured for nsub monitor diode n jtag interface for device access and arm code development (compatible with arm multi-ice) n all digital input pins 5 v tolerant. 2.2 read formats n cd-r n cd-rw n cd-da (red book) n cd-rom. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 3 of 74 philips semiconductors SAA7803 one chip cd audio device 3. ordering information 4. block diagram table 1: ordering information type number package name description version SAA7803h qfp100 plastic quad ?at package; 100 leads (lead length 1.95 mm); body 14 20 2.8 mm sot317-2 fig 1. SAA7803 top level block diagram 001aab745 digital decoder hf adc lf analog adcs i 2 s-bus audio out audio processing interface arm7 cpu (thumb) cd text decoder interrupt controller smiu ahb decoder interface channel decoder SAA7803 2 analog inputs ahb to vpb bridge 2 timers 4 kb ram 32 kb rom lcd driver i 2 c-bus i 2 s-bus uart gpio vpb bus system arm7tdmi-s microprocessor digital servo ahb servo interface audio dac line and headphone out analog laser driver servo ahb bus 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 4 of 74 philips semiconductors SAA7803 one chip cd audio device 5. pinning information 5.1 pinning fig 2. pin con?guration SAA7803h v ss(dacf) hf_mon v ss(dacb) v ssa1 buf_out_l monitor buf_out_r laser v dda3 lpower a_in_1/gpio0 tdo2/gpio31 a_in_2/gpio1 int/gpio30/rtck tx/gpio_ana tms2/pgio29 rx/gpio_ana tdi2/pgio28 sda v ddd2 scl v ssd2 v ssd1 sl reset_n fo v ddd1 ra seg0/gpio4 tms seg1/gpio5 tdi seg2/gpio6 v ddp3 seg3/gpio7 v ssp3 seg4/gpio8 lkill rkill v ssp1 dobm v ddp1 v4/cl16 moto2 moto1 tdo trst_n tck seg5/gpio9 seg6/gpio10 seg7/gpio11 seg8/gpio12 seg9/gpio13 v lcd sync sclk wclk data ef sdi seg10/gpio14 dac_rp seg11/gpio15 dac_rn seg12/gpio16 dac_vref seg13/gpio17 dac_ln seg14/gpio18 dac_lp v dd(led) v dd(dac) seg15/gpio19 oscin seg16/gpio20 oscout seg17/gpio21/cl1 v ssa2 seg18/gpio22/meas opu_ref_out seg19/gpio23/cflg v dda2 com0/gpio24 aux_r com1/gpio25 aux_l com2/gpio26 r2 scli v dda1 com3/gpio27 v ssp2 int_ex_rom v ddp2 wcli r1 d4 d3 d2 d1 001aab746 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 80 79 78 77 76 75 74 73 72 71 70 69 68 67 61 60 59 58 57 56 15 16 17 18 19 66 65 64 63 62 26 27 28 29 30 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 81 45 46 47 48 49 86 85 84 83 82 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 5 of 74 philips semiconductors SAA7803 one chip cd audio device 5.2 pin description table 2: pin description symbol pin type description v ss(dacf) 1 p audio dac ?oating ground v ss(dacb) 2 p audio dac and buffer shared ground buf_out_l 3 ao audio buffer left output buf_out_r 4 ao audio buffer right output v dda3 5 p positive supply voltage 3 for audio buffer a_in_1/gpio0 6 aibts analog input 1 or general purpose i/o 0 a_in_2/gpio1 7 aibts analog input 2 or general purpose i/o 1 tx/gpio_ana 8 aibts uart transmit or general purpose i/o rx/gpio_ana 9 aibts uart receive or general purpose i/o sda 10 b i 2 c-bus interface data i/o line (open drain output) scl 11 b i 2 c-bus interface clock line v ssd1 12 p digital core ground 1 reset_n 13 iuh power-on reset (active low) v ddd1 14 p digital core supply 1 lkill 15 btsu kill output for left channel (con?gurable as open drain) rkill 16 btsu kill output for right channel (con?gurable as open drain) v ssp1 17 p digital ground 1 for periphery (pads) dobm 18 os biphase mark output (no external buffer required) v ddp1 19 p digital supply 1 for periphery (pads) seg0/gpio4 20 aibts lcd segment drive or general purpose i/o 4 seg1/gpio5 21 aibts lcd segment drive or general purpose i/o 5 seg2/gpio6 22 aibts lcd segment drive or general purpose i/o 6 seg3/gpio7 23 aibts lcd segment drive or general purpose i/o 7 seg4/gpio8 24 aibts lcd segment drive or general purpose i/o 8 seg5/gpio9 25 aibts lcd segment drive or general purpose i/o 9 seg6/gpio10 26 aibts lcd segment drive or general purpose i/o 10 seg7/gpio11 27 aibts lcd segment drive or general purpose i/o 11 seg8/gpio12 28 aibts lcd segment drive or general purpose i/o 12 seg9/gpio13 29 aibts lcd segment drive or general purpose i/o 13 v lcd 30 p lcd supply voltage (5 v) seg10/gpio14 31 aobs lcd segment drive or general purpose i/o 14 seg11/gpio15 32 aobs lcd segment drive or general purpose i/o 15 seg12/gpio16 33 aobs lcd segment drive or general purpose i/o 16 seg13/gpio17 34 aobs lcd segment drive or general purpose i/o17 seg14/gpio18 35 aobs lcd segment drive or general purpose i/o18 v dd(led) 36 p led supply voltage (3.3 v) seg15/gpio19 37 aobs lcd segment drive or general purpose i/o 19 seg16/gpio20 38 aobs lcd segment drive or general purpose i/o 20 seg17/gpio21/cl1 39 aobs lcd segment drive or general purpose i/o 21 or clock output for sampling channel decoder telemetry outputs 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 6 of 74 philips semiconductors SAA7803 one chip cd audio device seg18/gpio22/meas 40 aobs lcd segment drive or general purpose i/o 22 or channel decoder telemetry output seg19/gpio23/cflg 41 aobs lcd segment drive or general purpose i/o 23 or channel decoder correction statistics com0/gpio24 42 aibts lcd back plane drive or general purpose i/o 24 com1/gpio25 43 aibts lcd back plane drive or general purpose i/o 25 com2/gpio26 44 aibts lcd back plane drive or general purpose i/o 26 com3/gpio27 45 aibts lcd back plane drive or general purpose i/o 27 v ssp2 46 p digital ground 2 for periphery (pads) int_ex_rom 47 id development rom select (low = internal rom) v ddp2 48 p digital supply 2 for periphery (pads) wcli 49 i serial word clock input (loopback) scli 50 i serial bit clock input (loopback) sdi 51 i serial data input (loopback) ef 52 bts c1 and c2 error ?ag data 53 ots serial data output wclk 54 bts word clock output sclk 55 bts serial clock output sync 56 ots efm frame synchronization v4/cl16 57 bts versatile pin 4 or clock output 16.9344 mhz v ssp3 58 p digital ground 3 for periphery (pads) v ddp3 59 p digital supply 3 for periphery (pads) tdi 60 iu jtag1 test data input tms 61 iu jtag1 test mode select tck 62 idh jtag1 test clock trst_n 63 iu jtag1 asynchronous reset (active low) tdo 64 ots jtag1 test data output moto1 65 ots motor output 1 moto2 66 ots motor output 2 ra 67 ots radial actuator fo 68 ots focus actuator sl 69 ots sledge actuator v ssd2 70 p digital core ground 2 v ddd2 71 p digital core supply 2 tdi2/gpio28 72 btsu jtag2 test data input or general purpose i/o 28 tms2/gpio29 73 btsu jtag2 test mode select or general purpose i/o 29 int/gpio30/rtck 74 bts external interrupt or general purpose i/o 30 tdo2/gpio31 75 bts jtag2 test data output or general purpose i/o 31 lpower 76 p laser power supply laser 77 p laser drive monitor 78 ai laser monitor diode table 2: pin description continued symbol pin type description 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 7 of 74 philips semiconductors SAA7803 one chip cd audio device [1] all digital inputs are ttl levels. all digital outputs are cmos levels. all digital inputs and bidirectional pins are 5 v tolerant. v ssa1 79 p analog ground hf_mon 80 ao hf monitor output signal v dda1 81 p analog supply d1 82 ai diode voltage input (central diode signal input) d2 83 ai diode voltage input (central diode signal input) d3 84 ai diode voltage input (central diode signal input) d4 85 ai diode voltage input (central diode signal input) r1 86 ai diode voltage input (satellite diode signal input) r2 87 ai diode voltage input (satellite diode signal input) aux_l 88 ai headphone buffer left input/auxiliary audio left input aux_r 89 ai headphone buffer right input/auxiliary audio right input v dda2 90 p analog supply voltage opu_ref_out 91 ao opu reference voltage v ssa2 92 p analog ground oscout 93 ao crystal or resonator output oscin 94 ai crystal or resonator input v dd(dac) 95 p audio dac positive supply dac_lp 96 ao audio dac left channel differential output (positive) dac_ln 97 ao audio dac left channel differential output (negative) dac_vref 98 aio audio dac decoupling point (10 m f and 100 nf in parallel to ground) dac_rn 99 ao audio dac right channel differential output (negative) dac_rp 100 ao audio dac right channel differential output (positive) table 3: pin type de?nition [1] type de?nition type de?nition ai analog input id digital input with pull-down aio analog input/output idh digital input with pull-down, hysteresis ao analog output iu digital input with pull-up aobs analog output, digital bidirectional, slew rate limited iuh digital input with pull-up, hysteresis b digital bidirectional os digital output bts digital bidirectional, 3-stateable, slew-rate limited ots digital output, 3-stateable, slew rate limited btsu digital bidirectional, 3-stateable, slew-rate limited, pull-up p power connection i digital input table 2: pin description continued symbol pin type description 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 8 of 74 philips semiconductors SAA7803 one chip cd audio device 6. functional description 6.1 analog data acquisition the input signals from the opu photo diodes contain information used in the servo loops and the high frequency data from which the audio samples are reconstructed. the SAA7803 contains all the necessary circuitry to process the photodiode signals directly and hence removes the need for a separate external diode signal preampli?er. 6.1.1 lf acquisition the lf signal path acquires the photodiode voltage signals and converts them into 4 mhz pulse density modulation (pdm) digital data streams. these streams are processed within the digital servo to control the focus, radial and sledge loops. the servo processing makes use of the difference calculations d1 - d2, d3 - d4 and r1 - r2. ideally these differences should be zero when the quantities are equal due to the laser illumination. however in a practical system, errors reduce the accuracy of the signal processing. two main forms of errors exist - dc offsets and relative gain mismatch between the difference channels. the dc offsets are minimized in SAA7803 by dc offset compensation circuitry which allows the dc present in the pdm streams to be measured when the laser is switched off, and then subtracted in the digital domain from the signals when the laser is on. relative gain mismatch is minimized by using carefully scaled circuitry in the time continuous parts of the signal path, and by time sharing circuitry in the time discrete parts. a simpli?ed block diagram of the lf acquisition path is shown in figure 3 . the output of the opu is converted to a current across the input resistor. the current conveyor provides a low input impedance and a high output impedance and sets a virtual earth at the end of the v-to-i converter to the same voltage as v ref (1.6 v). fig 3. lf acquisition 001aab747 internal reference 1 level shifter d1offset[32:1] lfadcgain[3:0] c int feedback switch feedback dac dc compensation dac v ref v i voltage-to-current converter current conveyor d1_pdm compin f sl (clock) comp_ref_sel[1:0] v dd internal reference 2 v ss 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 9 of 74 philips semiconductors SAA7803 one chip cd audio device the level shifters purpose is to act as a summing node for the dc cancellation and to produce a current that is referenced to an internal bias voltage and therefore independent of v ref . the output current charges an integration capacitor. when the voltage reaches v dda /2 the comparator switches and sends a feedback current that is in the opposite polarity to the input current to try to discharge the capacitor. the register lfadcgain de?nes the amount of feedback current and therefore sets the gain of the adc. the output of the adc is a pdm waveform which is passed through a low-pass ?lter (in the digital domain) and the average value at the output of the ?lter is in proportion to the voltage between v i and v ref . the same adc structures are used for the auxiliary analog inputs, aux_l and aux_r and the general purpose analog inputs, a_in_1 and a_in_2. the adcs used by the auxiliary analog inputs are multiplexed with the d1 and d2 inputs whereas the general purpose analog inputs have dedicated adcs. 6.1.2 hf acquisition the hf data (efm) signal is obtained by summing the signals from the three or four central diodes of the opu, ?ltering the signals and converting to a digital representation via a 6-bit rf adc. figure 4 shows a simpli?ed block diagram of the hf path. fig 4. hf acquisition g f e d c b a 001aab748 high-pass filter noise filter 6-bit rf adc rfpwd 20 k w 20 k w 20 k w 20 k w 20 k w 20 k w 20 k w 80 k w 80 k w single-ended to differential converter 4 hfadcpwd sys_clk rf_adc_out[5:0] sys_clk from pll rfmonsel[2:0] rfdiffpwd noisefreqsel[3:0] rfmonpwd offsetcompvalue[5:0] rfbypasssel d1 d2 d3 d4 hf_mon 82 83 84 85 80 20 k w 0 db to 24 db g1fixed[3:0] rf amp1 rf amp2 0 db to 12 db g2dyn[3:0] c a d e g f b rfbypasssel 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 10 of 74 philips semiconductors SAA7803 one chip cd audio device the four diode signals d1, d2, d3 and d4 are summed in the ?rst rf ampli?er. the gain of the ?rst ampli?er is controlled by g1fixed[3:0] (fixed = static), register agcgain, bits 7:4. a second gain stage has been added to lessen the gain bandwidth requirements of a single gain stage operational ampli?er and also to act with the dynamic automatic gain control (agc). the gain of this ampli?er is set with g2dyn[3:0] (dyn = dynamic) register agcgain, bits 3:0 and can be changed on the ?y from the arm microprocessor. the gain range was chosen to accommodate 12 db of gain needed to boost the signal as the laser tracks across a ?nger print defect on the disc. cd-r, cd-rw and ?nger prints not only reduces the ac signal amplitude compared to a perfect pressed disk, but also reduces the dc pedestal voltage. the high-pass ?lter will remove all dc present at the input but offsets would be added by the second and third gain stages. a 5-bit plus sign dac controlled by register offsetcomp, bits 5:0, offsetcompvalue[5:0] adds a current to compensate for this offset. the amount of current will reduce in linear db states and will track the ac gain. to help users of the ic setup the correct gain and dc offset for each particular mechanism, an eye pattern monitor facility has been included. this consists of a high frequency buffer ampli?er whose input can be selected to monitor various important nodes within the analog rf path. the monitor point is controlled by register rfcontrol1, bits 6:4 rfmonsel. the output of the buffer drives pin hf_mon (pin 80). this register also controls the roll-off frequency of the noise ?lter which precedes the 6-bit adc in the rf path. various blocks within the analog rf path can be powered down if required, including the complete path. these power-down bits are controlled by register rfcontrol2, bits 5:0. in addition, the 6-bit rf adc can be tested stand alone in application mode or a separate external rf path ic can be connected to SAA7803 by selecting bit 1 of register rfbypasssel. the input for the rf signal is then through pin hf_mon. in this mode the center diode summing circuit, rf amp1, high-pass ?lter and rf amp2 are all bypassed. 6.2 analog clock generation fig 5. analog clock generation 001aab749 mux divide by 2 mux 8 multiplier mux hf adc audio dac pad_clk1v8 sys_clk sysclk_premux adac_out_4_clk pad_clk oscin 94 93 oscout 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 11 of 74 philips semiconductors SAA7803 one chip cd audio device sys_clk is the primary clock used by the channel decoder and arm clock generators. this clock operates at 67 mhz with either an 8 mhz or 16 mhz crystal or resonator. the divide-by-2 is selected when a 16 mhz crystal or resonator is used. 6.3 general purpose analog inputs the two general-purpose adc inputs (a_in_1, pin 6 and a_in_2, pin 7) can be used for giving the arm microprocessor access to external analog sources, e.g. for monitoring temperature and to provide simple resistor-ladder keypad functionality. these inputs use an additional pair of sigma delta adcs identical to those used for the lf diode inputs. the general purpose analog inputs have separate interrupt request lines and use address space in the servo registers for storing the converted digital values. the output of the general-purpose adcs are low-pass ?ltered and can have ?ne offset compensation added before being passed to a decimation ?lter. the digital values from the decimation ?lter are then captured in the servo registers with 10-bit resolution per channel. see figure 6 . 6.4 auxiliary analog inputs two further analog inputs, aux_l and aux_r, are available with suf?cient resolution for inputting external audio sources, e.g. for allowing arm access to an external audio source for sound processing algorithms. this allows audio processing of external audio sources via the aux pins, whilst simultaneously using the general purpose inputs for keyboard and temperature inputs. fig 6. general purpose analog inputs block diagram 001aab750 sigma-delta adc dc offset compensation low-pass filter interrupt generator fine dc offset compensation decimation filter servo registers (10-bit) irq to arm microprocessor reg 2f8 for a_in_1 a_in_1 or a_in_2 6 or 7 reg 2fc for a_in_2 reg 318 for a_in_1 reg 31c for a_in_2 4 .com u datasheet
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 12 of 74 philips semiconductors SAA7803 one chip cd audio device fig 7. auxiliary analog input 001aab751 multiplexer s 1 s 2 c d dsic adc multiplexer s 1 s 2 c d multiplexer s 1 s 2 c d multiplexer s 1 s 2 c d d1 or aux l d2 or aux r low-pass filter d1 or aux l d2 or aux r d1 or aux l d2 or aux r headphone buffer dac lp or aux l dac rp or aux r decimation filters serial out vpb bus i 2 s-bus router 10-bit samples of aux l and aux r expanded to 16 bits by adding six lsbs spare reg a if_auxin_sel spare reg a buf_auxin_sel d2 83 3 4 aux_r buf_out_l buf_out_r 89 d1 82 aux_l 88 dac lp aux r d2 aux l d1 dac rp block used to route i 2 s-bus to audio dac or pins data bclk wclk 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 13 of 74 philips semiconductors SAA7803 one chip cd audio device since these two inputs share one pair of the lf sigma-delta adcs used in the lf path (for inputs d1 and d2) a multiplexer is used to control the data source into the adcs. for this reason, d1 and d2 cannot be used at the same time as aux_in_l and aux_in_r. a further multiplexer is used to switch the input pads from the headphone input buffer modes to auxiliary input modes. this path has a speci?cation of snr = 55 db and thd < 0.3 % and can be used for tuner input processing. these performance ?gures are below that available when the normal cd-audio path is used i.e. snr > 80 db and thd < 0.01 %. please ensure that the signal applied to the auxiliary inputs is bandwidth limited to 20 khz or aliasing may occur. the auxiliary inputs do have an adjustable second order anti-alias ?lter, but, please be aware that this may not provide enough stop band rejection in all cases. the audio data is converted to a pulse density modulated digital stream for both input channels. this data is then low-pass ?ltered and decimated to produce 10-bit representations of the analog inputs. the auxiliary input is different from the general purpose analog inputs in that the parallel data is converted to an i 2 s-bus format stream and then sent to the i 2 s-bus handler block which makes the data available to the arm microprocessor. the i 2 s-bus handler contains a variable size data fifo which means the arm microprocessor does not have to service the audio data with as high a priority as it would if it were directly registered. see figure 7 . 6.5 ahb core clock generation two independent clock dividers are used within SAA7803, one for cd-slim and the other for the arm advanced high performance bus (ahb) core. figure 8 gives a top level description of the SAA7803 clocking, ahb ?xed clock frequencies are given. a more detailed description of the cd-slim clocking is given in figure 10 . 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 14 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6 channel decoder 6.6.1 features the channel decoder in the SAA7803 is derived from the design used in the saa7817 dvd decoder ic. the design has been optimized for cd decode functionality (i.e. efmplus demodulation has been removed) and has the following features: ? 1-channel interface to the on-chip 6-bit 67 mhz ad converter ? signal conditioning logic with high-pass ?lter, dc offset cancellation (analog offset cancellation; aoc) and agc logic ? hf defect detection circuitry with automatic hold of agc, aoc, high-pass filter (hpf), pll and slicer on defect detection ? digital equalizer, noise ?lter, pll and slicer ? rl2pb mechanism ? efm demodulator with sync interpolation ? cd-text and subcode q-channel extraction blocks with software-interface via registers fig 8. clocking top level 001aab752 lcd ram arm rom smiu ahb/ vpb interface pdsic 8.4672 mhz pdsic clock cd-slim clock generator clock generator analog clock generator gpio interrupt controller uart i 2 c-bus i 2 s-bus handler audio dac vpb ahb oscin 94 93 ahb and vpb operate at arm frequency 67 mhz baseline clock 1.536 khz lcd clock 4.2336 mhz audio dac clock 9.6768 mhz i 2 c-bus clock i 2 s-bus bit clock arm/ahb/vpb clock oscout 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 15 of 74 philips semiconductors SAA7803 one chip cd audio device ? decoding, de-interleaving and reed-solomon error correction according to cd circ standards ? on-chip de-interleaving sram memory ? audio processing back-end with interpolate / hold, mute, kill and silence detect logic; and de-emphasis and 4 upsample ?lter ? two data-output interfaces: i 2 s-bus and ebu ? one serial subcode output interface ? motor control for clv or open loop or software controlled regulation with 1 or 2 motor pins (no onboard tacho) ? 8-bit register map; with ahb slave interface ? an interrupt output with associated interrupt, status and interrupt enable registers for full interrupt driven operation ? debug information available via pin meas, pin cflg and parallel debug-bus. 6.6.2 block diagram refer to figure 9 . the incoming diode signals are ?rst added and processed in the analog front-end in order to create a proper rf (hf) signal. this analog signal is converted to digital by the adc. this signal is then resampled from the adc clock to the system clock domain via the int/dump block. offset and gain on the rf signal are regulated via the agc/aoc loop (via the analog front-end). remaining offset which is not removed by the analog front-end can be removed via the digital hpf. the rf signal is then sliced by the bit detector. clock recovery is done by a full-digital pll with noise ?lter, equalizer and sample rate convertor. a defect detector makes it possible to hold agc, aoc, hpf, slicer and pll during black / white dots. at this point in the data path, rf-samples are converted into a bitstream. the rl2 pushback will avoid rl3s in the rf being accidently translated into rl1 or rl2 in the bitstream. the channel bit stream is demodulated to bytes by the efm demodulator. q-channel subcode and cd-text information is extracted via the q-subcode and cd-text decoder, available for readout through the subcpu interface. the main data stream is error-corrected by the erco, while the memproc takes care of the circ de-interleaving and buffering of data in a fifo. at the back-end of the channel decoder, corrupted audio-samples can be interpolated and held, while a burst of errors can trigger the mute block. detection of digital silence can be used to kill the internal / external audio dac. pre-emphasis on the audio-disc can be removed via the de-emphasis ?lter, and the data can be 4 upsampled before sending to the audio dac. cd-data is outputted via the i 2 s-bus and/or the ebu outputs. motor control can be frequency regulated on incoming rf bit rate, with additional phase regulation on fifo ?lling, or can be fully controlled via software. clv support is guaranteed in this way, cav support must be regulated and steered via software in open loop (no tacho available). debug information is available via registers, via the dedicated serial lines meas and cflg and via a parallel debug bus (not available when used in an application). 4 .com u datasheet
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 16 of 74 philips semiconductors SAA7803 one chip cd audio device the numbers next to each functional block refer to the local address (hexadecimal) of the registers that control speci?c logic. fig 9. channel decoder top level diagram 001aab753 analog adc int/dump hpf noise filter digital equaliser slice level determine rl2 pushback interrupts zero trans detect digital pll rms filter measurement offset measurement peak detector peak detectors agc aoc defect detector erco memproc (circ dec and fifo) interpolate / hold soft mute error detect silence detect kill generation de- emphasis upsample i 2 s-bus hard mute ebu motor control clock shop subcpu and general q-subcode efm demodulator cd-text src clocked on pll clock hold hold 120-128, 134-138, 148 multiplex 140-144 1d0, 1d8 1d8 1e0 1ec 1dc 1e8 1e8 1e0, 1e4 1f0 1f0 1e0 1f0 1d0, 1d4 jitter value pll frequency slice level error correction info meas 000 0a0 0d4-0d8 060-0a0 1b0-1bc 1a0-1a8 174, 180-184 170, 178 168 020, 240, 248, 24c 000-00c 210-22c 0d0 0a4-0bc 13c 12c 130 160 040-04c 0f0-104 to efm demodulator d1 to d4 from rl2 pushback 82 to 85 65 66 16 15 40 41 cflg i 2 s-bus lkill rkill moto2 moto1 ebu 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 17 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6.3 clock control the clock control block de?nes the clock frequencies for four clock domains. fig 10. clock control 001aab754 int and dump clocksys_div (pulse blanking) /1 (33 mhz), /2 (16 mhz), /4 (8 mhz), /8 (4 mhz) /16 (2 mhz) clockebu_div (50 %) /2, /3, /4, /6, /8, /12, /16, /24, /32, /48 cl16_div (50 %) /3, /4, /6, /8 clockbit_div (50 %) /2, /3, /4, /6, /8, /12, /16, /24, /32, /48 bdei cl1_div (50 %) /1, /2, /3, /4 cl1 sysclk sys_always_on phi1 phi2 phi3 fastclk ebuclki ebuclk cl16clock ebuclock sysclock cl1clock bitclock bclki cl16 bclk bclk_in xclk (67 mhz) adc_clk hf_clk (67 mhz) /2 33 mhz (50 %) 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 18 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6.3.1 signal xclk most internal clocks are derived from xclk. this clock is the output of the clock multiplier in the analog part and has a ?xed frequency of 67.7376 mhz = 8.4672 (crystal oscillator) x 8. if a 16 mhz crystal is used, the crystal clock is divided by 2 inside the analog block. crystal selection is done via anaclockpllcontrol(sel16). 6.6.3.2 sysclock domain the main part of the internal channel decoder blocks run on the sysclk or derivatives. sysclk is derived from xclk divided by 2 (50 % duty cycle) and can be further divided down via register sysclockcon?g(sysdiv). this register also provides the possibility to power-down the majority of the clocks (for sleep mode).the choice of the sysclk frequency in an application is determined by the expected input bit rate on the rf stream. the relation between this incoming bitstream frequency f bit and the system clock is expressed in a f bit /f sysclk ratio. there are 2 limiting factors: ? the hf-pll operation range is between 0.25 f bit /f sysclk and 2 f bit /f sysclk . ? the decoder and error corrector throughput rate is limited to 1.7 f bit /f sysclk . this brings the constraint to 0.25 < f bit /f sysclk < 1.7 6.6.3.3 bit clock domain the i 2 s-bus back-end logic runs on this clock. bclk is also output as part of the i 2 s-bus interface. in audio slave mode this clock needs to be programmed exactly at 44100 2 16/24/32 hz (depending on i 2 s-bus-mode), to get a 1 data rate to the audio dac. in master mode with gated bclk, bclk must be programmed at a higher rate than the required outgoing bit rate for that disc speed, to avoid fifo over?ow in the decoder. (for instance at n =1, the incoming rf bit rate is 4.3218 mhz, which corresponds to an output bit rate of 1.4112 mhz. this means that bclk > 1.4112 mhz is high enough when i 2 s-bus-16 is chosen, while i 2 s-bus-32 requires at least 2.8224 mhz bclk. the bclk division is selected via register bitclockcon?g. also bclk gating can be enabled via the same register. 6.6.3.4 ebu clock domain the ebu back-end runs on this clock. the ebu (or spdif) interface is only enabled during audio slave mode. the ebuclk needs to be exactly 44100 64 = 2.8224 mhz for 1 operation. ebuclk division is selected via register ebuclockcon?g. there are a few other clocks controlled by the clock control block: ? the hf_clk is ?xed at 67.7376 mhz, and is used to clock in the samples from the adc, which is clocked by the xclk with the same clock frequency ? the bclk_in is the incoming i 2 s-bus bit clock, which is used when i 2 s-bus is programmed to receive bclk rather than transmitting it (programmed via register iiscon?g) ? the cl1 clock can be used to monitor the cflg and meas debug lines; the frequency can be programmed via register clclockcon?g ? the cl16 clock can be used to clock an external audio dac or audio ?lter ic; the frequency can be programmed via register clclockcon?g. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 19 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6.4 decoder to arm microprocessor interface the decoder core is internally connected to the arm core via the ahb interface for register access to the decoder internal con?guration registers. 6.6.4.1 programming interface decoder registers are programmed through the ahb interface. (a full description of the interface itself is not described in this document.) for the application, it should be noted that the interface supports 32-bit registers, while the decoder only contains 8-bit registers. as a result, the decoder registers are treated as 32-bit registers of which the 24 msbs are not used. the register address map occupied by the decoder are from relative address 000h to address 374h, and can be split in 2 parts: 000h - 24ch; the decoders own registers, which are used to con?gure the channel decoder; the functionality they control is described in detail in this section 2a0h - 374h; the decoder immigrant registers, which are not used to control the decoder channel decoder; they control other parts of the SAA7803, which do not have their own ahb interface. 6.6.4.2 interrupt strategy the channel decoder contains 2 interrupt registers. interruptstatus1 contains all interrupts that operate as set / reset latches (set by hardware, reset by reading from the register). interruptstatus2 contains all interrupts that operate as feedthroughs (set by hardware, reset by hardware or by accessing other registers). every interrupt bit can be enabled or disabled separately by writing to the corresponding enable bit in the interruptenable1 and interruptenable2 registers. if one or more interrupt bits in the status registers are set, and at least one of them has its corresponding enable turned on, the interrupt line of the decoder to the microprocessor will go active (low). when an interrupt bits corresponding enable is turned off, the interrupt status bit will behave the same as described above, the difference is that it will not trigger the interrupt line. in this mode the interrupt could still be processed if polling on the status register is used rather than real interrupt handling in the microprocessor. 6.6.5 efm bit detection and demodulation a block diagram of the bit recovery is shown in figure 11 . the hf signal is combined from the 4 diode inputs inside the analog block. it is preprocessed (lpf, hpf, offset removal and gain adjustment) and then sampled by a 6-bit adc. fig 11. bit recovery analog block d1 d2 d3 d4 6-bit adc agc aoc signal conditioning block 001aab755 to demodulator pll and bit slicer 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 20 of 74 philips semiconductors SAA7803 one chip cd audio device on the sampled hf, bit recovery is done by a full digital pll and slicer. before the sampled signal enters the pll section, it is preprocessed by a signal conditioning block. this consists of an integrate and dump block, a high-pass ?lter and logic for gain control and offset control on the rf-signal in the analog section. for good playability on defects, a defect detector is used to hold the pll, slicer, agc, offset cancellation and high-pass ?lter during defects. the detected bits are then sent to the demodulator for sync extraction and efm demodulation. for playing on damaged or out-of-spec disks, ?ywheels are used to make the sync extraction more robust. 6.6.5.1 signal conditioning this device has a number of blocks which process the incoming 6-bit hf-signal: ? integrate and dump block to adapt the frequency of the ad converter to the system clock ? peak detection logic for amplitude measurement ? peak detection logic for dc offset measurement ? digital high-pass ?lter with con?gurable cutoff frequency ? dc and gain control logic for on-board variable gain and offset control (in the analog section) ? a defect detector. all blocks can be con?gured under microprocessor control. integrate and dump block: the adc delivers one sample every xclk period (equal to one sample every hf_clk period). the sample rate needs to be adapted from this xclk rate to the lower sysclk rate. for more information on sysclk speed, see section 6.6.3 cloc k control on page 17 . fig 12. signal conditioning 001aab756 hf-data to bit detection hold signals to bit detection hold analog adc int/ dump peak detector defect detector agc aoc peak detector high-pass filter offset measurement 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 21 of 74 philips semiconductors SAA7803 one chip cd audio device the integrate and dump block converts the incoming samples at the hf_clk frequency into a stream of one sample per sysclk period. it averages a number of samples to achieve this. if the division factor for the system clock is 2, 4, 8, 16, or 32, an average of 2, 4, 8, 16 or 32 incoming samples is taken and passed on further. the result is a gain in the number of effective bits of the analog-to-digital conversion. high-pass ?lter: a ?rst order iir high-pass ?lter with a variable 3 db point is implemented. this can be used to ?lter the remaining dc jump on defects (analog hpf will have ?ltered off most). the cutoff frequency of the digital high-pass ?lter can be changed on the ?y, by writing to register highpassfiltcont. it is possible to reset the state of the high-pass ?lter, via bit 6 of register highpassfiltcont. the input and the output of the high-pass ?lter is 8 bits wide. the high-pass ?lter is implemented in a 1 minus low pass structure. it is possible to hold the low-pass ?lter on defects. for more information, see section def ect detector on page 25 . the high-pass ?lter is driven by the system clock. its bandwidth is also proportional to the sysclk. an approximate formula for the cutoff frequency, f c , of the high-pass ?lter is peak detectors: there are 2 types of peak detectors present in the signal conditioning block. the ?rst type works on an immediate attack / slow decay basis, and is used for measuring peaks, amplitude and offset for readback by software sending peak information to the defect detector. the second type works on the principle of detecting maximum and minimum peaks within a window, and is used for the agc and aoc control logic. both sets of peak detectors will look at the rf after it has passed an optional noise ?lter. this noise ?lter is an lpf with a programmable high cutoff frequency. this bandwidth is programmed via register pdbandwidth(noisefilterbw) for the noise ?lter before the peak detectors of agc/aoc and measurement read back. the defect detector peak detector has its own noise ?lter which is programmed via register defectdetpeakbw(noisefiltbw). peak detector with decay ?lter: the functional schematic of this peak detection is shown in figure 13 . f c hpf , hpset 5:0 [] 2 p 2 11 ----------------------------- f sysclk = 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 22 of 74 philips semiconductors SAA7803 one chip cd audio device the minimum and maximum peaks of the incoming signal are measured. switch s1 takes the largest value at its inputs. switch s2 takes the minimum value at its inputs. the time constant of the decay ?lters has to be long. the same bandwidth is used for the decay ?lters of both the minimum and maximum peak detectors. the decay ?lter for the maximum peak responds to the smallest value possible. the decay ?lter for the minimum peak responds to the largest value possible. the decay bandwidth of the measurement readback decay ?lter is controlled via register pdbandwidth(decaybw), the bandwidth of the defect detector is controlled via register defectdetpeakbw(decaybw). the following settings of the decay ?lters are possible: c = 1 - 2 - m , for m = 6 to 21, where m = decaybw[3:0] + 6. the corresponding bandwidths of the decay ?lter are shown in t ab le 4 , when the frequency of the system clock is 10 mhz. peak detector based on window: the functional schematic of this peak detection is shown in figure 14 . fig 13. peak detection diagram with decay ?lter table 4: time constants of the decay ?lters, at sysclk = 10 mhz m t ( m s) m t ( m s) m t (ms) m t (ms) 6 6.35 10 102.4 14 1.64 18 26.21 7 12.75 11 204.7 15 3.28 19 52.43 8 25.55 12 409.6 16 6.55 20 104.8 9 51.15 13 819.2 17 13.11 21 209.7 fig 14. peak detection diagram with window 001aab757 s1 maxpeak minpeak noise filter hf_in s2 c c 001aab758 noise filter hf_in maxpeak minpeak window width 0 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 23 of 74 philips semiconductors SAA7803 one chip cd audio device the minimum and maximum peaks of the incoming signal are measured during a programmable window period. the highest and lowest value samples within this window are used to update maxpeak and minpeak. the window width of the measurement is controlled via agcaoccontrol(pdmeaswindow). agc and aoc control block: the agc control block controls the rf amplitude at the input of the adc by controlling the gain of an on-chip analog gain ampli?er. the aoc control block controls the rf offset at the input of the adc by adding or subtracting offset just before the adc. both agc and aoc loops are built up in the same manner and are pictured in figure 15 with their relative position within the signal conditioning block. first, the maximum and minimum peaks on the envelope of the rf signal after the adc are measured via a noise ?lter and the window peak detector (see section p eak detectors on page 21 ). after that, the amplitude is calculated as maxpeak - minpeak, and the offset as (maxpeak + minpeak) / 2. for tuning the loops, it is possible to read back the hfmaxpeak, hfminpeak, hfamplitude and hfoffset, as measured by the decay peak detector, from registers. agc control: the rf-amplitude at the adc input can be changed with 2 gain ampli?ers in the analog part: g1 (?xed) and g2 (dynamic). g1 has a gain-range from 0 db to 24 db in 16 steps of 1.6 db, while g2 has a range from 0 db to 12 db in 16 steps of 0.8 db. both gains can be programmed via register agcgain. g1 will stay ?xed, while g2 can be regulated in hardware as soon as the agc is turned on. the agc will regulate the gain such that the measured amplitude stays between a programmed upper threshold (agcthrhi) and lower threshold (agcthrlo). if amplitude is smaller, gain will increase; if amplitude is too large, gain will decrease. whenever clipping is detected on one or two sides, gain will decrease as well. these gain changes are not sent to the analog gain ampli?er directly, but are integrated over time. only if on average a gain increase or decrease is requested, this will result in a real gain increase or decrease on the ampli?er (the gain can also be read back via register agcgain). fig 15. agc and aoc loops 001aab759 high-pass filter (analog) integrator clipping detect adc i/d high-pass filter (digital) window peak detect decay peak detect noise filter (low-pass) noise filter (low-pass) decay peak detect registers defect detect g1 g2 g3 to bit detection k-offset 6 msbs software/ defect integrator k-gain 4 msbs software/ defect hi lo hi lo + 1 - 1 - 1 + 1 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 24 of 74 philips semiconductors SAA7803 one chip cd audio device together with the noise ?lter on the peak detector this prevents noise occurring on the rf which would result in volatile gain regulation. to decrease volatile behavior even further a hysteresis window with a width of one gain step has been added between the integrator and g2. the bandwidth of the gain loop will determine how fast it reacts on ?ngerprints and scratches, and can be programmed via register agcintegbw. it is also possible to limit the range of g2 by programming a maximum and minimum boundary (in register agcgainbound). aoc control: most rf-offset at the adc input will be removed by the analog hpf (?rst order hpf with 3 db point around 3.6 khz). the remaining offset (mainly introduced by the analog front-end itself), can be removed by adding or subtracting a ?xed offset in the analog part. this offset subtraction or addition has a range of 32 steps in each direction, with approximately 1.4 lsbs per step (referenced to the rf-adc). this leads to a full correction range of 42 lsb steps (more then the whole adc range). this offset compensation value can be programmed via register offsetcomp, and will be regulated in hardware as soon as the aoc is turned on. the aoc will regulate the offset compensation value such that the measured offset stays within a programmed window (offsetbound). if offset is above this window, offsetcompvalue will decrease; if it is below, it will increase. if an inversion occurs on the rf signal between analog and digital, this reaction of the loop can be inverted by programming offsetbound(offsetinv). these offset changes are not sent to the analog offset subtraction directly, but are integrated over time. only if on average an offset increase or decrease is requested, this will result in a real offset increase or decrease on the analog addition (can also be read back via register offsetcomp). together with the noise ?lter on the peak detector this prevents noise occurring on the rf which would result in a volatile offset regulation. to decrease volatile behavior even further a hysteresis window with a width of one offset step has been added between the integrator an offsetcompvalue. the bandwidth of the offset loop will determine how fast it reacts on ?ngerprints and other defects, and can be programmed via register offsetintegbw. it is also possible to limit the range of the offsetcompvalue by programming a maximum and minimum boundary (in register offsetcompboundhi and offsetcompboundlo). agc and aoc in general and rules of thumb: the agc and aoc hardware regulation loops can be enabled and disabled separately by register agcaoccontrol. this register also allows the use of a slow agc and / or aoc loop. in that case the programmed loop bandwidth is decreased with an extra factor of 128. in this mode the loops will be too slow to react on defects, but can be used for a slow software-like gain and / or offset regulation to regulate the average gain and offset over the disc nicely within a speci?ed range. an important feature is the agcaoccontrol(disholdnolock) bit, which disables holding of the agc and aoc loops during defects (triggered by the defect detector, see section def ect detector ) while the hf-pll is not in lock. this feature avoids permanent lockups of the loops caused by a small amplitude triggering the defect detector, which in turn would hold the agc loop. as rule of thumb, the following should be taken into account: the amplitude thresholds should be programmed not too close to each other, to allow at least 2 gain steps (1.6 db) to go from lower to higher boundary and vice versa. this is to avoid a volatile agc. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 25 of 74 philips semiconductors SAA7803 one chip cd audio device the offset boundary should be programmed not too tight, 8 is a good value. this is to avoid a volatile aoc. the bw of the loops should never be programmed too high (fast) with respect to the peak detector measurement window, to avoid an unstable loop. if the pdwindow = 2 n sysclks wide, the bw of the loops should never be higher than 2 - (n+1) . defect detector: the purpose of the defect detector is to detect the presence of black or white dots in the rf-stream, and to freeze some signal conditioning and bit recovery logic during these defects. this will prevent the control loops drifting away from their optimal point of operation whilst there is no rf present, so they can recover quickly when good rf is present again. the detection of a defect is based on amplitude. the amplitude is measured via a set of peak detectors with decay, as described in section p eak detectors on page 21 . the programming of the decay bandwidth and noise ?lter bandwidth is done by register defectdetpeakbw. two thresholds can be programmed. a low threshold will trigger a defect-detected signal as soon as amplitude goes below this threshold. a high threshold will clear this defect-detected signal again as soon as amplitude goes above this threshold. together these thresholds add an hysteresis to the defect detection, which avoids a jittery defect-detected signal (switching on/off many times) when amplitude is on the edge. thresholds are programmed in register defectdetthres. the defect-detected signal can be used to hold the pll, slicer, agc, aoc and hpf during a defect. which feature(s) will be held can be programmed in register defectdetenables. the same register can be used via software to force the pll, slicer and hpf into hold mode. the agc and aoc can be held in software by just disabling the loops in register agcaoccontrol. two special features exist on the defect detector: ? it is possible to delay the enabling and disabling of hold features at the beginning and end of a defect. this can be done by programming a start and / or stop delay (in number of sysclks) via register defectdetstartstopdelay. whenever the defect detector detects the start of a defect, the detector will wait for the start delay before triggering a defect-detected-processed signal. when the defect detector detects the end of a defect, the detector will wait for the programmed stop delay before clearing the defect-detected-processed signal again. this also means that defects which are smaller than the start delay are ignored and, that if the defect contains zones with good rf amplitude but smaller than the stop delay, they are ignored as well. in reality all hold features are triggered by the defect-detected-processed signal, rather than the defect-detected signal; but after rest of the decoder, both delays are zero, so both signals are equal. ? it is possible to program a time-window after the end of a defect, during which higher pll and / or slicer bandwidths can be used (to speed-up the recovery of these loops after the defect). this window can be programmed via register defectdethighbwdelay, the programming of the bandwidths is explained in section 6.6.5.2 bit detector on page 26 . the detection of the beginning or end of a defect, with and without start and stop delays, can be used to generate an interrupt. this is programmed in register interruptenable1. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 26 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6.5.2 bit detector the bit detector block contains the slice level circuitry, a noise ?lter to limit hf-efm signal noise contribution, an equalizer, a zero-transition detector, a run length pushback circuit, a digital pll and jitter measurement logic. all processing is done using the bit clock, and bandwidths are proportional to the channel bit rate. to achieve this, rf data is resampled in the system clock domain to the bit clock domain by using a sample-rate convertor. blocks can be con?gured under microprocessor control and are described in detail in the next paragraphs. noise ?lter: the digital noise ?lter runs on the channel bit clock frequency f b . it will limit the bandwidth of the incoming signal to 1 4 of the channel bit clock frequency: pass band: 0f b to 0.22f b stop band: 0.28f b to (f b - 0.28f b ) rejection: - 28 db. slice level determination: the slice level determination circuit compensates the incoming signal asymmetry component. bandwidth of the slice level determination circuit is programmable via register slicerbandwidth. also the higher bandwidths for use after a defect (see section def ect detector ) are programmed in this register. the bandwidth is proportional to the channel bit clock frequency. the slice level, or asymmetry, can be read back via register slicerassym. equalizer: in the bit detection circuit, a programmable equalizer is used, it boosts the high frequency content of the incoming signal. a ?ve-tap presentable, asymmetrical equalizer is built in. the equalizer block diagram is given in figure 17 . fig 16. bit detection noise filter digital equalizer slice level determine rl2 pushback zero transition detect digital pll rms jitter measurement src clocked on pll clock multiplex jitter value pll frequency slice level meas to demodulator from signal conditioning - 40 001aab760 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 27 of 74 philips semiconductors SAA7803 one chip cd audio device the ?rst and last tap can be programmed via register pllequaliser. usable efm bit clock range: the channel bit clock frequency should always obey the following constraints: it should be less than 2 f sys it should be larger than 0.25 f sys or: 0.25 < f sys < 2. only in this range a reliable bit detection is possible. if input channel bit rate is above 2 f sys then the pll will saturate to two times the system clock frequency f sys . remark: while these are theoretical limits, a real-life application should keep a safety margin. when the bit clock is relatively low, the internal ?lter will ?lter off more noise, yielding a better performance. if the theoretical upper limit is approached, playability (e.g. black dot performance) will drop signi?cantly. the decoder will only be able to correct the biggest correctable burst error of 16 frames if f bit /f sys < 1.7. taken this restriction on the decoder into account, the range is: 0.25 < f bit /f sys < 1.7. digital hf pll: the digital pll will recover the channel bit clock. the capture range of the pll itself is very limited. to overcome this dif?culty, two capture aids are present. when using automatic locking, the pll will switch state based on the difference between expected distance and actual distance between syncs. in total, three different pll operation modes exist: in-lock (normal operation); the pll frequency matches the frequency of the channel bits with an accuracy error less than 1 % inner lock aid (capture aid 1); the pll frequency matches the frequency of the channel bits with an accuracy error between 1 % and 10 % outer lock aid (capture aid 2); the pll frequency deviates more than 10 % from the channel bit frequency. first, pll operation during in-lock is explained. this is the normal on-track situation. after this, the lock-detection and the two capture aids are explained. pll in-lock characteristics: the pll behavior during in-lock can best be explained in the frequency domain. pll operation is completely linear during in-lock situations. the open-loop response of the pll (bode diagram) is given in figure 18 . fig 17. equalizer 001aab761 a 1 a 1 d d d d d in -- + out 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 28 of 74 philips semiconductors SAA7803 one chip cd audio device the frequencies f 0 , f 1 and f lpf are programmable using register pllbandwidth. the higher bandwidths for use after a defect (see section def ect detector on page 25 ) are programmed in register pllbandwidthhigh. when the pll is in-lock the recovered pll clock equals the channel bit clock. detection of pll lock: the pll locking state is determined by the distance between detected syncs. this means that the sync detection is actually doing the control of the automatic pll locking. the pll switches from outer lock to inner lock when successive syncs are detected to be 588 25 channel bits apart. internally this is also called a winsync (sync falls in a wider window). the number of missed winsyncs is kept in a 3 bit con?dence counter, and the pll will go out of outer lock when 7 consecutive out-of-window syncs are found. the pll switches from inner lock to in-lock when successive syncs are detected 588 1 channel bits apart. the number of consecutive missed syncs is kept in a bit counter, and saturates on either 16 or 61, depending on the value of bit lock 16 or 61 in register demodcontrol. when the saturation level is reached, the pll is set out of lock. the pll frequency (inner) and phase (in) lock status can be read out in register plllockstatus. pll outer lock aid: the outer lock aid has no limitation on capture range, and will bring the pll within the range of the inner lock aid. the pll will ?rst regulate its frequency based on detecting rl3s as the smallest possible rls (fast but rough regulation), and next on detecting rl11s as the largest possible rls (slow but more accurate). pll inner lock aid: the inner lock aid has a capture range of 4 %, and will bring the pll frequency to the phase-lock point. it will regulate the pll frequency such that 588 bits are detected between 2 efm-syncs. f 1 : integratorxover; controlled via k i . f 0 : pllbandwidth; controlled via k p . f lpf : lpbandwidth; controlled via k f . fig 18. pll bode diagram 001aab762 f 0 f 1 f lpf frequency loop gain 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 29 of 74 philips semiconductors SAA7803 one chip cd audio device in?uencing pll behavior: programmability and observability is built into the pll mainly for debugging purposes, and also to make dif?cult applications possible. the pll operation can be in?uenced in two ways. first, it is possible to hand-select the state the pll is in (in-lock, inner lock, outer lock, outer lock with only rl3 regulation). second, it is possible to pre-set the pll frequency to a certain value. overruling the plls state: pll state can be: ? in-lock ? inner lock ? outer lock ? outer lock with rl3 regulation only ? hold. normally, selection is done automatically using the lock detectors. selection can be overruled via register plllockaidcontrol. when lockmode is left to 0, user can still select lockstate, but hardware will overwrite this if hardware selected lockstate means closer to lock. remark: during pll hold the frequency will not change and the frequency pre-set may be used. writing the pll frequency: it is possible to preset the pll frequency to a certain value. this is done by writing the integrator value of the pll in register pllintegrator. the relationship between the bit frequency, the integrator value, and the sysclk frequency is given by: the real-time value of the pll frequency can be read on the same address. 6.6.5.3 limiting the pll frequency range the range over which the pll can capture the input frequency can be limited. the minimum and maximum pll frequencies are set in bits minintfreq respectively maxintfreq of register pllminmaxbounds. table 5: pll states lockmode plllockcontrol meaning 0 00000 automatic lock behavior 1 00001 force hf pll into in-lock 1 00110 force hf pll into inner lock aid 1 00100 force hf pll into outer lock aid 1 01000 force hf pll into hold mode 1 10100 force hf pll into outer lock aid with rl3 regulation only x others reserved f channelbit pllfreq 7:0 [] 4 + 128 --------------------------------------------- - f sysclk = 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 30 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6.5.4 run length 2 pushback detector if this circuit is switched on, all run length 1 (rl1) and run length 2 (rl2) symbols (invalid run lengths) are pushed back to run length 3 (rl3). for rl2s, the circuit will determine the transition that was most likely to be in error, and shift transition on that edge. this feature should always be turned on, but can be deselected via register rl2pushback. 6.6.5.5 available signals for monitoring the operation of the bit detector can be monitored by the microprocessor and using an external pin. several signals are made available for measurement. pll frequency signal: the ?rst signal that can be monitored is the pll frequency signal. monitoring via the microprocessor is done by reading the register pllintegrator. asymmetry signal: the second signal that can be monitored is the 8-bit asymmetry signal. the signal is in 2-complement form and can be read from register slicerassym. jitter signal: a jitter measurement is done internally. the zero-crossing jitter is available in register plljitter. the jitter measurement is done in two steps. first, the distance between the efm zero transition and the bit clock zero transition is measured. second, the calculated jitter for the zero transition is averaged using a 10-bit low-pass ?lter. the top 8 bits of the ?lter output can be read back from register plljitter. to obtain the jitter in % of the channel bit clock, the following formula applies: % this jitter measurement is also available via the telemetry signal on pin meas. on this signal, the full 10-bit output of the ?lter is available - see section 6.6.5.6 f or mat of the measurement signal on meas pin . it is also possible to read out an average jitter value via register pllaveragejitter. this value is an average over a period of 8000 bit clocks on the normal jitter value. the formula to transform this into % is the same: % table 6: jitter input calculation distance ( f bit ) average distance (bit clocks) jitter ?lter input (5-bit decimal integer) < 2 16 1 16 1 2 16 to 4 16 3 16 9 4 16 to 6 16 5 16 25 > 6 16 7 16 49 jitter jitter 7:0 [] 2.83 C 1024 ------------------------------------------- 100 = average jitter average jitter [7:0] 2.83 C 1024 ------------------------------------------------------------------ 100 = 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 31 of 74 philips semiconductors SAA7803 one chip cd audio device use of jitter measurement: the jitter measurement is an absolute-reference jitter measurement. it gives the average square value of the bit detection jitter. the jitter is measured directly before the bit detection in this device, and contains contributions due to various imperfections of the complete signal path: (note that bit-to-clock jitter is measured.) ? disc ? analog preampli?er ? ad converter ? limited bandwidths in this device ? limited pll performance ? in?uenced by internal noise ?lter, asymmetry compensation, equalizer. the jitter measurement is absolute-reference, because it relates directly to the efm bit error rate if the disc noise is gaussian. internal lock ?ags: the fourth signal that can be monitored are three ?ags in the plllockstatus register: the internally generated inner lock signal flock, the internally generated lock signal inlock and a longsym(bol) ?ag when run length 14 is detected. (too high run length). in automatic mode, the flock and inlock ?ags determine what type of pll capture mode is used. 6.6.5.6 format of the measurement signal on meas pin on this serial bus, which is output via pin meas and should be monitored using cl1 (available via another pin), three measurement signals are multiplexed together. figure 19 gives details on the format. the data is sent in a serial format. it consists of a pause, followed by a start bit. the start bit is followed by data bits. the bit length is four system clock periods, the frame length is 64 bits and the data format is shown in t ab le 8 . table 7: determining the current pll capture mode flock flag inlock flag capture mode 0 0 outer lock aid 1 0 inner lock aid x 1 in-lock fig 19. signal format on measurement pin meas 001aab763 pause start bit data bits 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 32 of 74 philips semiconductors SAA7803 one chip cd audio device [1] the start bit is always preceded by 17 pause bits. the intermediate start bits at bit locations 12, 24 and 36 guarantee that no other '1'-value is preceded by 17 '0'-bits. this allows a simple start bit detection circuit. [2] the jitter word is sampled twice in every frame. the jitter in % is calculated with the following formula: % 6.6.5.7 demodulator the demodulator block performs the following functions ? efm demodulation using a logic array ? sync detection and synchronization ? sync protection. 6.6.5.8 efm demodulation each efm word of 14 channel bits (which are separated from each other by three merging bits) is demodulated into one data byte using the standard logic array demodulation as described in the cd red book. 6.6.5.9 sync detection and synchronization the efm sync pattern is a unique pattern which is not used anywhere else in the efm data stream. it consists of 24 bits: rl11 - rl11- rl 2. an internal sync pulse is generated when two successive rl11s are detected. a subsync pulse occurs when the beginning of a new subcode frame is seen. this is done by analyzing the subcode information: when two successive subcodes are subcode-sync-code s0 and s1, subsync will be activated. 6.6.5.10 sync protection the subsync pulse is protected by an interpolation counter, this counter uses the fact that a subcode frame is always 98 subcode symbols long. the sync signal itself is also interpolated. if after 33 data bytes (= 1 efm-frame), no new sync is detected, it is assumed that the bit detector has failed to correctly achieve it, and the sync signal is generated anyway, this is generally called an interpolated sync. if table 8: data format on measurement pin meas bit number value description note 0 1 start bit [1] 1 to 10 jitter[9:0] ?rst sample of jitter word [2] 11 0 12 1 intermediate start bit 13 to 22 pllfreq[9:0] pll frequency word 23 0 24 1 intermediate start bit 25 to 32 asym[7:0] slicer level 33 to 35 0 36 1 intermediate start bit 37 to 46 jitter[9:0] second sample of jitter word [2] 47 to 63 0 pause jitter jitter 9:0 [] 12.81 C 4096 ---------------------------------------------- 100 = 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 33 of 74 philips semiconductors SAA7803 one chip cd audio device furthermore a new sync is detected in the data shortly after a previous sync signal (interpolated or real) no new sync signal will be generated, because this means the frame has slipped. after enough data byte periods, the sync signals are allowed to pass again. there is a small chance it is possible to detect false syncs, causing corrupted efm bits to form by accident in the combination rl11-rl11. if two (or three) of such false syncs are detected at the correct distance from each other, this would cause a false resync of the demodulator. such resync could lead to a large number of samples being corrupted at the output of the circ decoder. chance of false sync detection is highest during defects (black and white dots). to prevent such false demodulator resyncs, two features have been built in, which are both programmable via register demodcontrol: ? robustcntresync; this feature should always be turned on; when it is on, the demodulator will look for three (instead of two) consecutive syncs with correct in-between distance before resyncing; this will improve robustness to false syncs substantially ? syncgating; when 1, the sync-detection is turned off during a defect, to avoid the detection of false syncs; when 0, sync detection is left on all the time; it should be noted that the defect detector needs to be setup properly before this feature can be used; therefore this feature is turned off by default after reset. 6.6.6 cd decoding 6.6.6.1 general the decoder block performs all processing related to error correction and circ de-interleaving and uses an internal sram fifo which provides the necessary data capacity for doing this. it also extracts the q-channel subcode and the cd-text information from the data stream and delivers it to the application via a register interface. 6.6.6.2 q-channel subcode interface the channel decoder contains an internal buffer which stores the q-channel bytes of a cd-subcode-frame. this subcode can be retrieved by the microprocessor by accessing the registers subcodeqstatus, subcodeqdata and subcodeqreadend. to start retrieving the subcode, the microprocessor must read the register subcodeqstatus ?rst. this register contains various status bits that indicate the status of the q-subcode that may be read. when, after reading the register subcodeqstatus, the qready bit is found 1, the q-subcode interface will be blocked (indicated by qbusy going to 1) to prevent a new subcode overwriting the current one. bit qcrcok indicates if the current subcode frame had correct data content by a hardware crc check. after reading subcodeqstatus with qready = '1', the microprocessor may retrieve as many subcode bytes as required (max. 10) by issuing subsequent reads to register subcodeqdata. the content of the q-channel subcode in the main data area is described in t ab le 9 . for description of the content during the lead-in area, see cd red book. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 34 of 74 philips semiconductors SAA7803 one chip cd audio device after ?nishing subcode read the microprocessor must release the interface to allow the decoder to capture new subcode information. this is done by issuing a read to register subcodeqreadend. the availability of a new subcode frame will also trigger an interrupt if bit interruptenable2(subcodereadyenable) is set. 6.6.6.3 cd-text interface the channel decoder contains an internal buffer which stores cd-text information (format 4, available in the lead-in area). the buffer can hold one cd-text pack for readback, while it receives at the same time the next pack. the operation of the cd-text readback interface is controlled via register cdtextcontrol. bit freezeen determines whether or not the internal buffer is frozen during readback (such that the next pack can not overwrite the current one before the microprocessor has ?nished reading). bit crcfailen determines whether or not packs with a failing crc check are made available for readback. this subcode can be retrieved by the microprocessor, by accessing the registers cdtextstatus, cdtextdata and cdtextreadend. to start retrieving the cd-text pack, the microprocessor must read the register cdtextstatus ?rst. this register contains various status bits that indicate the status of the cd-text pack that may be read. when, after reading the register cdtextstatus, the textready bit is found 1, the cd-text interface will be blocked (indicated by textbusy going to 1) to prevent new subcodes overwriting the current one; at least if cdtextcontrol(freezeen) is turned on. bit textcrcok indicates if the current cd-text pack had correct data content by a hardware crc check. after reading cdtextstatus with textready = '1', the microprocessor may retrieve as many cd-text bytes as required (maximum 16) by issuing subsequent reads to register cdtextdata. after ?nishing cd-text read the microprocessor must release the interface to allow the decoder to capture new cd-text information. this is done by issuing a read to register cdtextreadend. table 9: subcode q-channel frame content address/byte name description remark 1 control/mode 2 tno 3 point 4 rel min mod100 relative time 5 rel sec mod 60 6 rel frame mod 75 7 zero 0 or incremented modulo 10 8 abs min mod100 absolute time 9 abs sec mod 60 10 abs frame mod 75 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 35 of 74 philips semiconductors SAA7803 one chip cd audio device remark: if cdtextcontrol(freezeen) is disabled, the interface is not held during readback, which means that the current cd-text pack can be overwritten by the next one before all bytes of the current pack are read out. such an event will be indicated by setting cdtextreadend(bufferoverflow) to 1, so that it can be noticed by software at the end of the pack-read. the availability of a new cd-text pack will also trigger an interrupt if bit interruptenable1(cdtextreadyenable) is set. 6.6.6.4 main data decoding data processing: the cd main data is de-interleaved and error-corrected according the cd red book circ decoding standards and uses an internal sram as buffer and fifo. the c1 correction will correct up to two errors / efm-frame, and will ?ag all uncorrectable frames as an erasure. the c2 error correction will correct up to two errors or four erasures, and will also ?ag all uncorrectable frames as an erasure. the decoding operation is controlled by the decomode register. there are basically two decode operation modes: ? in ?ush mode, the de-interleaver tables are emptied, and all internal pointers are reset. no data is written into the buffer, no corrections are done, and no data is output ? in play mode, de-interleaver tables are ?lled, c1 / c2 corrections are done, and data is output (when available). during ?ush mode, no data is output from the device. during play mode, data is output via the i 2 s-bus interface as soon as it is available in the internal fifo. figure 20 shows the operation of the fifo and corrections during cd playback. de-interleaving of the data is done in accordance with the red book speci?cation. de-interleaving is performed by the sram fifo address calculation functions in the memory processor. two corrections are done - c1 followed by c2. data latency and fifo operation: the system data latency is a function of the minimum amount of data required in the fifo to perform the de-interleaving operation. the latency is quoted in the number of c1 frames (24 bytes of user data). the latency of the circ decoder is 118 frames. fig 20. data processing during cd mode 001aab764 fifo filling data from demod 'd' de-interleave 'd' de-interleave delta de-interleave c1 correct c2 correct fifo to i 2 s-bus back-end 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 36 of 74 philips semiconductors SAA7803 one chip cd audio device the fifo ?lling is de?ned as this data latency plus the number of extra frames stored in the fifo. the ?lling of the fifo must be maintained within certain limits. 118 frames is the minimum required for de-interleaving and 128 is the physical maximum limit determined by the size of sram used. this results in a usable fifo size of 11 frames. the status of fifo ?lling can be read back via register fifofill. the fifo ?lling must have a correct value. this can be achieved in 2 ways: ? master (flow control) mode: this mode is selected when using a gated bit clock (bclk) at the i 2 s-bus interface, see section 6.6.7.9 i 2 s-b us interf ace on page 41 for more information. as soon as a frame is available in the fifo, it is output via the i 2 s-bus interface. when fifo under?ow is imminent, the decoder will gate off the output interface by disabling bclk. ? slave (audio) mode: in this case, the bit clock is continuously clocking. the application is responsible for matching the input rate (efm bit rate coming from the disc) to the selected output rate (i 2 s-bus bclk speed), and keeping fifo ?lling between 118 and 128. this is done by regulating the disc speed. see section 6.6.8 motor on page 44 for more details. the fifo is only storing data, not subcode. this means that the data will be delayed as it comes from the demodulator, but the subcode is sent straight over the i 2 s-bus interface. the difference in delay between subcode and data is always ?xed. it is absolutely ?xed in master mode, but can have small local variations during slave mode. safe and unsafe correction modes: the cd circ decoding standard uses a reed-solomon error correction scheme. reed-solomon error correction has always a very small chance of miscorrection, which means that a corrupted codeword is modi?ed into a valid but wrong codeword. the chance of such miscorrections increases exponentially for every extra byte that needs to be corrected in a codeword, and is the highest when doing the maximum number of corrections possible with a certain reed-solomon correction scheme. miscorrections should be avoided, since they will result in corrupted data being sent to the back-end, without their corresponding invalid ?ag being set. certainly for cd-audio this is a problem, since un?agged wrong data will not get interpolated, which can result in audible clicks. both c1 and c2 correction logic can be programmed to operate in an unsafe or safe mode via register ercocontrol. in unsafe mode, the maximum number of corrections will always be done (if required). in safe mode, corrections will not be done when they are considered at risk, which means there is a realistic chance they could lead to a miscorrection. for c1, unsafe mode will allow two bytes per codeword to be corrected, safe mode only one. for c2, both modes will allow up to four erasures per codeword to be corrected. when there are more then four erasures and therefore erco switches back to error correction, unsafe mode will allow two bytes to be corrected, safe mode only one. remark: from experiments and theory it is advised to use c1 unsafe and c2 safe for cd-audio as a good trade-off between safety and maximum error correction capability. for cd-rom c1unsafe and c2unsafe can be used, if there is at least a c3 error correction and if the ?yhweels in the cd-rom block decoder are robust to possible invalid but un?agged headers. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 37 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6.6.5 error corrector statistics cflg: the error corrector outputs status information on the cflg pin. the format of this information is serial, similar to that used on the meas pin. the serial format consists of a pause bit followed by a start bit. this start bit is followed by the data bits. the format of the data is explained in t ab le 10 . the bit length is 7 sysclk periods and the frame length is 11 bits. [1] the repetition rate on the cflg signal is not ?xed. may be longer or shorter depending on disc speed and output interface speed. there is always at least one pause bit. [2] cormode de?nition: 000: c1 correction 011: c2 correction 100: corrector not active others: not used [3] corfail and flagfail indicate failure status on previous codeword [4] errorcount indicates the number of errors found in the chien search. bler counters: there is also a set of two bler counters which count the number of frames (c1 / c2) with at least one error (for c2, erasures coming from c1 will also be counted). it doesnt matter whether the frame was correctable or not. these registers are reset on read, and the user is responsible for reading them in regular intervals. the bler counters can be read on c1bler and c2bler. 6.6.7 audio back-end and data output interfaces the channel decoder back-end is shown in figure 21 . table 10: format description of cflg serial bus bit no value meaning note 0 1 start bit [1] 1 to 3 cormode[2:0] type of correction [2] 4 flagfail failure ?ag set because correction at risk [3] 5 corfail failure ?ag set because correction impossible [3] 9 and 6 to 8 errorcount[3:0] number of errors corrected [4] 10 0 pause bit [1] 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 38 of 74 philips semiconductors SAA7803 one chip cd audio device decoded and error corrected cd-data streams into the audio back-end from the memory processor to the output interfaces. some audio ?ltering can also be done (in case of playing cd-da). 6.6.7.1 audio processing the following audio features are present at the back-end: ? interpolate / hold for i 2 s-bus and ebu ? soft mute for i 2 s-bus and ebu ? hard mute for ebu ? de-emphasis ?lter for i 2 s-bus ? upsample ?lter for i 2 s-bus ? error detection ? silence detection ? kill generation. some status bits concerning these audio features can be read back via register mutekillstatus. 6.6.7.2 interpolate and hold on cd audio disks with many (large) defects, where c1 / c2 correction can not correct all errors, the audio data can be interpolated / held, to avoid audible clicks and plops when playing back the disk. this feature is enabled by setting filtercon?g(interpolateen). the principle is depicted in figure 22 . fig 21. back-end audio functions memproc interpolate/ hold soft mute error detect silence detect de-emphasis upsample i 2 s-bus 001aab765 kill generation hard mute ebu ebu i 2 s-bus left kill right kill 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 39 of 74 philips semiconductors SAA7803 one chip cd audio device audio samples ?agged as uncorrectable, neighbored by 2 good samples - or a held and a good sample, will be interpolated. audio samples ?agged as uncorrectable, which are not followed by a good sample, will hold the previous (correct or held) sample value. this feature is enabled or disabled for i 2 s-bus and ebu together. 6.6.7.3 soft mute and error detection the audio data going to the i 2 s-bus and/or ebu interface can be processed by a soft mute block. this block can ramp the audio volume down from 0 db to - 90 db, making use of 64 stages of about 1.5 db each. the current stage can be monitored and changed in software by reading or writing register mutevolume. this allows the implementation of a software mute-scheme. if the hardware mute logic is triggered by the error detection block (see section 6.6.7.4 ), it will ramp the volume down from maximum till fully muted in 3/n ms, with n the x-rate of the disc. the mute logic can be enabled separately for the i 2 s-bus and ebu outputs, by setting the corresponding bits in register mutecon?g. the back-end also contains an error detection block, that scans the data for a programmable number (via register muteondefectdelay) of consecutive corrupted stereo samples. if such a pattern is found, and mutecon?g(muteerren) is turned on, the softmute will be triggered to start its volume ramp down. this detection will also trigger a interruptstatus1(audioerrordetected) interrupt. 6.6.7.4 hard mute on ebu the ebu can be hard muted (ebu main data and ?ags set to 0, status and user channel still valid) by setting ebucon?g(ebuhardmute). 6.6.7.5 silence detection and kill generation the silence detector looks for 250 ms of digital silence (2s complement data = all 1s or all 0s) on either one or both channels and can trigger the kill-logic when it is found. enabling of this feature is done via killcon?g(killsilenceen). the kill-logic generates a left and a right kill signal, which are brought out of the channel decoder and can be used to gate the left and the right channel of an audio dac. the kill signals can be triggered on both channels together by the detection of stereo-silence, or on each channel separately by the detection of mono-silence. which operation is active depends on the setup in register killcon?g. it is also possible to set the left and right kill signals in software by writing directly to the killleft and killright bits in this register. fig 22. error concealment on cd audio 001aab766 ok error ok error error hold error ok ok interpolation interpolation 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 40 of 74 philips semiconductors SAA7803 one chip cd audio device another condition that will set both left and right kill signals is the soft mute block reaching fully muted (volume-stage 0). 6.6.7.6 de-emphasis ?lter this feature only affects the i 2 s-bus, not the ebu output. the de-emphasis ?lter can be used to remove pre-emphasis from tracks which have been recorded making use of the standard emphasis as described in the cd red book. the de-emphasis ?lter has the inverse response of the emphasis characteristics as described in the standard; see figure 23 . control over the de-emphasis ?lter is done via filtercon?g(deemphcontrol). the ?lter can be enabled or disabled under software control, or be fully automatic in hardware. in the latter case, the ?lter will be turned on when a pre-emphasis bit is detected in the control byte of the q-channel subcode, and turned off when this bit is missing. there are two possible detection modes: ? according to red book; only a pre-emphasis bit is checked (so is allowed to change) during the lead-in area, and during pauses between tracks ? according to orange book; pre-emphasis is checked on every subcode frame. 6.6.7.7 upsample ?lter (four times) this feature only affects the i 2 s-bus, not the ebu output. when it is enabled, the audio data will be upsampled by a factor of four. the upsampling provides the frequency response described in t ab le 11 . fig 23. de-emphasis characteristics 001aab767 t = 50 m s (3.18 khz) t = 15 m s (10.6 khz) frequency (khz) - 10 db 0 db gain (db) table 11: upsample ?lter frequency response pass band stop band attenuation 0 khz to 9 khz - 0.001 db 9 khz to 20 khz - 0.03 db - 24 khz 3 25 db - 24 khz to 27 khz 3 38 db - 27 khz to 35 khz 3 40 db 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 41 of 74 philips semiconductors SAA7803 one chip cd audio device when upsampling is enabled, the audio data output rate on the i 2 s-bus interface will be four times higher than without upsampling. therefore the i 2 s-bus word clock (pin wclk) frequency has to be four times higher. this means that the i 2 s-bus bit clock (bclk) speed needs to be programmed to be four times higher speed then normally required for that bit-rate when upsampling would be disabled. another result of the upsampling is that every sample will have 18 bits precision instead of 16 after the upsample ?lter. to make use of this extra bit-precision, the user should select 24-bit or 32-bit i 2 s-bus format. when using 16-bit i 2 s-bus format, the two lowest bits will not be output. 6.6.7.8 data output interfaces there are three interfaces via which data can be output from the channel decoder block. ? main data can be output via i 2 s-bus ? subcode can be output via the subcode interface ? main data + subcode can be output via ebu/spdif. all interfaces can be used at the same time if needed, although there are a few restrictions on the ebu, see section 6.6.7.10 eb u interf ace on page 42 . 6.6.7.9 i 2 s-bus interface the i 2 s-bus is a 6 wire interface (four main and two subcode). it supports 16-bit, 24-bit and 32-bit i 2 s-bus and eiaj (sony) modes. timing is shown in figure 24 . the required format can be selected in register iisformat. - 35 khz to 64 khz 3 50 db - 64 khz to 68 khz 3 31 db - 68 khz 3 35 db - 69 khz to 88 khz 3 40 db table 11: upsample ?lter frequency response continued pass band stop band attenuation fig 24. i 2 s-bus format 1; 16 clocks per word 001aab768 d0 d15 d14 d13 flag - msb (1 is unreliable) left right flag - lsb flag - msb d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 data bclk ef wclk sync 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 42 of 74 philips semiconductors SAA7803 one chip cd audio device compliant with the i 2 s-bus speci?cation, the i 2 s-bus signals wclk, data, ef and sync are all clocked on the falling edge of the i 2 s-bus bit clock signal bclk: ? bclk: all other i 2 s-bus signals are clocked on bclk ? wclk: indicates the start of a new 16/18-bit word on the data line, and differentiates between left and right sample ? data: 16/18-bit data words are outputted via this line, 1-bit / bclk-period ? error flag (ef): contains the byte reliability ?ag; bytes that are indicated as erasures (possible errors) after c1 and c2 correction, are ?agged. ? sync: indicates that the serial subcode line contains the msb of a subcode word; it will be asserted every six wclk periods for half a wclk period. if a subcode sync is transferred on the subcode line, this signal will be asserted for a full wclk period. the i 2 s-bus interface can either work in master or slave mode. in master mode, the bclk can be gated off by the channel decoder. in slave mode, the bclk is continuously running. to prevent the internal fifo from over?ow, the ?lling of the buffer must be regulated (see section data latency and fifo oper ation on page 35 ). bclk and wclk can either be input (generated outside the channel decoder) or output (generated internally in the clock control block). selection can be done via bits wclksel and bclksel in register iiscon?g. the i 2 s-bus output rate is determined by the speed of the bclk, which is con?gured via register bitclockcon?g. the i 2 s-bus interface can be con?gured to run at 1 or 2 cd. in case of gated bit clock, when bitclockcon?g(bclkgen) is 1, the speed must be con?gured such that the maximum rate available on the bus is 20 % higher than the average data throughput rate. or in other words: the bus should have at least 20 % idle time in between 2 bursts of data. default after reset, the i 2 s-bus pins on the ic will be put into 3-state. they can be activated via register iiscon?g. this register also contains the possibility to kill the i 2 s-bus interface, such that all data line outputs go low. 6.6.7.10 ebu interface the channel decoder contains a digital one wire ebu or spdif output interface. it formats data according to the iec60958 speci?cation. the ebu rate can be selected to be 1 or 2 cd, by programming register ebuclockcon?g. for proper operation of the ebu interface, the i 2 s-bus bit clock must be internally generated, bit clock gating must be disabled and the following relationship between ebuclk, bclk, wclk and i 2 s-bus format must be true: ebuclk = wclk 64 some ?elds in the user channel of the ebu-stream can be ?lled in by software, con?gured via register ebucon?g. bit iiscon?g(killebu) contains the possibility to kill the ebu interface, so that the line outputs go low. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 43 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6.7.11 subcode interface subcode data is output via the iissubo (pin v4) port. this data can be sampled using the i 2 s-bus sync signal (see section 6.6.7.9 i 2 s-b us interf ace on page 41 ). the sync indicates that the serial subcode line iissubo contains the msb of a subcode word. it will be asserted every six wclk-periods for half a wclk-period. if a subcode sync is transferred on the subcode line, this signal will be asserted for a full wclk period. during normal operation (upsampling disabled), the subcode output via iissubo will have the format as shown in figure 25 . when upsampling is enabled, the i 2 s-bus interface will run at four times the non upsampled rate. the subcode bit period however will stay at the non-upsampled rate as shown in figure 26 . this means that the iissubo and sync signal will appear to be four times slower relative to the wclk. in this case the receiver must use the wclk divided by four to sample the subcode. when slave mode is used, without bclk gating, it is also possible to use the iissubo output port as a true single-line interface. in that case the receiver needs to sample the data on the line with a frequency equal to f wclk 2 (since subcode is output at a rate of one bit per half wclk). two characteristics of the interface can be used in this case to synchronize the bit and byte detection in the stream in the absence of a sync signal: ? the ?rst bit (p-bit) of a subcode-byte is used as a start-bit and therefore always 1, (so no real p-channel information is available on the interface). between two subcode bytes there are four zero-bits; this can be used to identify the start of the subcode bytes within the stream. fig 25. subcode output; upsampling disabled 001aab769 wclk iissubo sync b6 b5 b4 b3 b2 b1 b0 1 subcode byte every 24 i 2 s-bus bytes b7 (start) b6 b5 b4 b7 (start) fig 26. subcode output; upsampling enabled 001aab770 wclk iissubo sync s0 b7 (start) b6 b7 (start) b6 b5 s0 s1 2 upsample wclk periods (0.5 non upsample wclk period) 24 upsample wclk periods (6 x non upsample wclk periods) 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 44 of 74 philips semiconductors SAA7803 one chip cd audio device ? the subcode syncs s0 and s1 are presented as all zeros on the interface (even p-channel), such that the last subcode byte of a subcode-frame, and the ?rst byte of the next frame are separated by 28 zero-bits. this can be used to identify the start of the subcode-frames within the stream. 6.6.8 motor a block diagram of the motor interface is given in figure 27 . the motor interface consists of a pi ?lter and a pdm/pwm modulator. when put in a closed loop, the motor controller can control both speed, frequency and position error (fifofill). it can be operated as a p, i or pi controller, by switching on and off the appropriate switches ( sw1 and sw2 ). the frequency and position error integrator gain, k i and k f , and gain g are programmable. frequency and ?lling set points are also programmable. the frequency input source can be selected between pll frequency and 0 hz. the position input source is always fifo ?lling. when operated in a stable operation point in closed loop, the motor controller will regulate the frequency input source and the fifo ?lling to their respective set points, this is implemented by speeding up or slowing down the motor by changing the dc content in the pdm/pwm output motor signals. all motor parameters can be con?gured by programming the motor registers. 6.6.8.1 frequency set point when operating the motor in clv mode, based on efm, for a certain overspeed, the motor frequency set point to be programmed is given by where f sys is the system clock frequency and n the overspeed factor. fig 27. motor servo 001aab771 m int pdm/pwm modulator sw1 k l k i _mult sw2 filling setpoint 0 pll frequencey fifo filling frequency setpoint k f k f _mult overflow detect 24 t delay preset/readback analog output stage gain motor g g e overflow detect 65, 66 moto1, moto2 + + - - motor frequency set point 7:0 [] 256 1 n 4.3218 10 6 2.667 f sys ----------------------------------------- - C ? ?? = 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 45 of 74 philips semiconductors SAA7803 one chip cd audio device the set point can be programmed via register motorfreqset. the selection of the motor frequency input is programmed via motorgainset2(motorfreqsource). 6.6.8.2 position error the position error will be used to ?ne tune the motor speed during slave mode, where the incoming efm bit rate is locked on the programmed ?xed i 2 s-bus bclk output speed. the set point must be chosen between 118 and 128, since this is the usable fifo size in the decoder. see section data latency and fifo oper ation on page 35 for more information. the set point can be programmed via register motorfifoset. 6.6.8.3 motor control loop gains (k p , k f and k i ) the control loop gains are all programmable through registers motorgainset1 and motorgainset2. to be able to set integrator bandwidth low enough at high system clock speeds an extra divider for the factors k i and k f is added. these factors can be written through the register motormultiplier. the resulting k i(tot) is then the k i multiplied by k i _mult. the resulting k f(tot) is then the k f multiplied by k f _mult. the integrator bandwidth must be scaled with the same factor k i _mult. please note the following: ? k f _mult operates by sampling the input; e.g. for k f _mult = 1, every sample of the input is passed through the integrator circuit, for a k f _mult of 0.5, every second sample is passed through, for a k f _mult of 0.25, every fourth sample is passed through, and so on ? for a dc input signal, k f k f _mult should always give the same result. if however, the input varies quickly, the k f k f _mult combinations with the same product will not always give the same result, especially for low values of k f _mult, where the sampling in the extreme becomes 1 out of every 128 samples. (the input samples to the block that performs the k f _mult multiplication occur at a rate of 1 sample every 24 system clock periods.). sub-sampling might affect the actual resulting gain. 6.6.8.4 operation modes the motor controller mode is programmed via register motorcontrol. it can operate in open loop by just sending a ?xed power to the motor for start-up and stopping, closed loop, or shut down. it also selects between pdm and pwm format. motor start and stop modes will put a ?xed duty cycle pwm or ?xed density pdm signal on the motor outputs. during start or stop, motor speed can be monitored by reading motorintlsb and motorintmsb. motorov: when not setting the appropriate gains in the loop, an over?ow might occur inside the pdm/pwm modulator block, or in the programmable gain stage. this is signalled by the motorov interrupt, which can be read back on interruptstatus2. the interrupt disappears when the over?ow disappears. motorov can also automatically open sw1 and sw2 . this is enabled by writing a 1 to bit ovfsw in register motorcontrol. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 46 of 74 philips semiconductors SAA7803 one chip cd audio device 6.6.8.5 writing and reading motor integrator value it is possible to obtain the integrator value by reading the registers motorintlsb and motorintmsb. the integrator can be written at the same location. by opening all switches, the user can bypass the whole control and ?lter part, and just use the block as a dac for the motor drivers. the control part can then be done in software. 6.6.8.6 some notes on application motor servo the motor servo can be used to control the motor during clv playback and also during cav or pseudo-clv lock-to-disc or jump mode. ? in clv mode, both sw1 and sw2 must be closed ? in cav / pseudo-clv mode, sw2 must be open and sw1 may be open ? the motor servo will revolve the disc at the speed corresponding to the frequency set point; in clv mode with lock to efm, the frequency set point must be set equal to the desired readout frequency of the hf-pll ? accelerating the disc must be done in one of the start modes ? braking the disc must be done in one of the stop modes. 6.7 digital servo - pdsic the digital servo block on SAA7803 is an evolution of the design used for the saa7824 ic, and is referred to as parallel digital servo ic (pdsic). the parallel description refers to the microprocessor interface to the servo block; this is now a high speed parallel interface, whereas it was previously a serial interface (e.g. saa7824 3/4 wire, i 2 c-bus). the other features of the pdsic are: ? programmable adc for cd-rw playback compatibility ? diode signal processing ? signal conditioning ? focus and radial control system ? access control ? sledge control ? shock detector ? defect detector ? off-track counting and detection ? automatic closed-loop gain control available for focus and radial loops ? high level features. 6.7.1 pdsic registers and servo ram control the servo block is controlled by two parts of the design - the servo control registers which are used to control the writing of commands and parameters to the servo; and the servo ram. the servo ram has two roles: storage of the servo parameters and capture of commands and parameters during the command process. all of the servo write commands consist of a command byte followed by a number of parameter bytes (between 1 and 7), all of which have to be loaded into the pdsic using a serial communication interface. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 47 of 74 philips semiconductors SAA7803 one chip cd audio device the command byte is the ?rst to be loaded and can be considered as two nibbles. the upper (most signi?cant) nibble represents the command itself whilst the lower (least signi?cant) nibble tells the pdsic how many parameter bytes to expect. the command byte gets placed into memory location 31h (called oldcom). subsequently, parameter bytes get loaded sequentially and these get placed into a stack space that has been reserved within the memory (locations 30h to 2bh). with each parameter byte that is loaded, the value in oldcom is decremented. in other words, the byte count decreases until it reaches 0, then the pdsic knows it has a complete servo command with a command byte and its full complement of parameter bytes. at this point, the pdsic acts upon the command and the appropriate function is carried out based upon the values in the stack space. there are two special case servo commands: write_parameter (opcode = a2h) and write_decoder_reg (opcode = d1h). write_parameter allows the microprocessor to write directly to any memory location. it carries two parameter bytes; the memory address and the data that is to be written. when this command is executed the command byte is loaded into oldcom and the ?rst parameter byte () is loaded onto the stack. the second parameter byte () is loaded directly into the location speci?ed by . write_decoder_reg allows decoder registers to be written to when the i 2 c-bus interface is being used. this command carries only one parameter byte, which is the decoder register / data pair (2 nibbles). when this command is received by the pdsic, the register / data pair is loaded into memory location 4dh. the servo read commands operate slightly differently in that they carry no parameter bytes and the lower nibble of the command byte is always 0 to indicate this. when the pdsic receives a read command it will make certain information available (mostly from memory, although some status information is retrieved from the decoder) on the serial interface for collection by the microprocessor. if a sequence of values are being read from the servo ram (e.g. a series of values related to a pid loop), it is important to ensure that the values are consistent with each other, i.e. to ensure the servo has not updated some of the values during the period they are read. therefore, an interrupt signal is available from the servo to the arm which raises an irq when it is safe to read related values. this can also be monitored by the state of the servo register bits srv_fc0 and srv_fc1 shown in t ab le 13 . the interrupt generator monitors these signals and raises an irq whenever the correct state is achieved. applying a pulse to the inreq_clr register bit will then clear the interrupt. if the interrupt is not cleared, it will automatically be reset when the valid reading state is no longer true. figure 28 shows the operation of the irq signal. int #1 shows the full duration of an interrupt that does not get cleared by the arm. int #2 and int #3 are shown being cleared by pulses being written to the inreq_clr register. the time between interrupts is approximately 15 m s and the total interrupt cycle time is approximately 60 m s. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 48 of 74 philips semiconductors SAA7803 one chip cd audio device from a system perspective, the simplest con?guration provides an lf path that is equivalent to the hardware servo (dsics) of the other audio devices such as saa7826, which uses the onboard hardware servo controller logic. however, an alternative setup will provide additional ?ne dc-offset compensation (in addition to the coarse compensation already found in the analog adcs) and the potential for full software servo control via the arm microprocessor. 6.7.2 diode signal processing the photo detector in conventional two-stage three-beam compact disc systems normally contains six discrete diodes. four of these diodes (three for single foucault systems) carry the central aperture (ca) signal while the other two diodes (satellite diodes) carry the radial tracking information. the ca signals are summed into an hf signal for the decoder function and are also differenced (after analog to digital conversion) to produce the low frequency focus control signals. the low frequency content of the six (?ve if single foucault) photodiode inputs are converted to pdm bit streams by a multiplexed 6-bit adc followed by a digital pdm generation circuit. this supports a range of opus in voltage mode mechanisms by having sixteen selectable gain ranges in two sets, one set for d1 to d4 and the other for r1 and r2. 6.7.3 signal conditioning the digital codes retrieved from the adc and pdm generator are applied to logic circuitry to obtain the various control signals. the signals from the central aperture diodes are processed to obtain a normalized focus error (fe) signal: where the detector set-up is assumed to be as shown in figure 20 . fig 28. function of servo irq signal 001aab772 natural duration of irq (~45 m s) int #1 int #2 int #3 irq cycle time of ~60 m s irq cycle time of ~60 m s irq cycle time of ~60 m s irq #2 cleared by inreq_clr pulse irq #3 cleared by inreq_clr pulse srv_fc0 srv_fc1 irq inreq_clr fe n d1 d2 C d1 d2 + --------------------- d3 d4 C d3 d4 + --------------------- C = 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 49 of 74 philips semiconductors SAA7803 one chip cd audio device in the case of a single foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows: the error signal, fe n , is further processed by a proportional integral and differential (pid) ?lter section. an internal ?ag is generated by means of the central aperture signal and an adjustable reference level. this signal is used to provide extra protection for the track-loss (tl) generation, the focus start-up procedure and the dropout detection. the radial or tracking error signal is generated by the satellite detector signals r1 and r2. the radial error (re) signal can be formulated as follows: where the index s indicates the automatic scaling operation which is performed on the radial error signal. this scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces the radial bandwidth spread. furthermore, the radial error signal will be made free from offset during start-up of the disc. the four signals from the central aperture detectors, together with the satellite detector signals generate a track position indicator (tpi) which can be formulated as follows: where the weighting factor sum_gain is generated internally by the SAA7803 during initialization. fig 29. detector arrangement fe n 2 d1 d2 C d1 d2 + --------------------- = re s r1 r2 C () re_gain r1 r2 + () re_offset + = tpi sign d1 d2 d3 d4 +++ () r1 r2 + () sum_gain C [] = d3 d1 d2 satellite diode r1 satellite diode r2 d1 d3 d2 d4 satellite diode r1 satellite diode r2 d1 d2 d3 d4 satellite diode r1 satellite diode r2 single foucault astigmatic focus double foucault mbg422 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 50 of 74 philips semiconductors SAA7803 one chip cd audio device 6.7.4 focus servo system 6.7.4.1 focus start-up five initially loaded coef?cients in?uence the start-up behavior of the focus controller. the automatically generated triangular voltage can be in?uenced by 3 parameters; for height (ramp_height) and dc offset (ramp_offset) of the triangle and its steepness (ramp_incr). for protection against false focus point detections, two parameters are available which are an absolute level on the ca signal (ca_start) and a level on the fe n signal (fe_start). when this ca level is reached then focus has been achieved. when focus is achieved and the level on the fe n signal is reached, the focus pid is enabled to switch on when the next zero crossing is detected in the fe n signal. 6.7.4.2 focus position control loop the focus control loop contains a digital pid controller which has 5 parameters that are available to the user. these coef?cients in?uence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, part of foc_parm1) action of the pid and a digital low-pass ?lter (foc_pole_noise, part of foc_parm2) following the pid. the ?fth coef?cient foc_gain in?uences the loop gain. figure 30 shows the transfer function of the controller, and the coef?cients which determine the behavior. a simpli?ed block diagram of the focus pid system is given in figure 31 . fig 30. bode diagram of focus pid system frequency (log hz) foc_lead_length foc_pole_lead foc_pole_noise 001aab773 foc_int foc_int_strength i p d amplitude (db) foc_gain w 5 w 1 w 2 w 3 w 4 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 51 of 74 philips semiconductors SAA7803 one chip cd audio device by using a zero error signal, the actuator position can be held. this action is taken if a defect or shock is encountered. the pid is followed by a low-pass ?lter to reduce audible noise in the control loop. the desired frequencies for the loop ( w 1 to w 4 ) are used to calculate the coef?cient values. full tables are given in the hardware software interface (hsi) speci?cation . an explanation of the parameters in these diagrams is given in t ab le 12 . [1] refer to table 3 of the hsi speci?cation . 6.7.4.3 dropout detection this detector can be in?uenced by one parameter (ca_drop). focus will be lost and the integrator of the pid will hold if the ca signal drops below this programmable absolute ca level. when focus is lost it is assumed, initially, to be caused by a black dot. 6.7.4.4 focus loss detection and fast restart whenever focus is lost for longer than approximately 3 ms, it is assumed that the focus point is lost. a fast restart procedure is initiated which is capable of restarting the focus loop within 200 ms to 300 ms depending on the programmed coef?cients of the microprocessor. 6.7.4.5 focus loop gain switching the gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. the integrator value of the pid is corrected accordingly. the differentiating (foc_pole_lead) action of the pid can be switched at the same time as the gain switching is performed. fig 31. functional diagram of focus pid system table 12: focus pid parameters [1] parameter controlled by comment w 1 - focus integrator bandwidth w 2 - beginning of focus lead w 3 foc_parm1 foc_pole_lead; end of focus lead (differentiating part) w 4 foc_parm2 foc_pole_noise; low-pass function following pid w 3 / w 2 foc_parm3 foc_lead_length; lead length (proportional part) w 5 = ( w 1 . w 2 / w 3 ) foc_int_strength integrator strength g foc_gain focus loop gain g e end stage gain de?ned as peak-to-peak voltage swing over focus actuator 001aab774 focus error, fe n p i d zero on defect or shock 1/j w j w / w 3 1 + j w / w 3 w 2 / w 3 w 1 w 4 g 68 fo focus actuator g e 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 52 of 74 philips semiconductors SAA7803 one chip cd audio device 6.7.4.6 focus automatic gain control loop the loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. this gain control injects a signal into the loop which is used to correct the loop gain. since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). 6.7.5 radial servo system 6.7.5.1 radial pid - on-track mode when the radial servo is in on-track mode (i.e. normal play mode), a pid controller is active for the fast actuator, while the sledge is steered using either a pi or pulsed-mode system. a simpli?ed diagram of the radial pid system is given in figure 32 : an explanation of the different parameters is given below. the frequency response of this system is given in figure 33 : [1] refer to table 2 of the hsi speci?cation . fig 32. functional diagram of radial pid system 001aab775 p d i j w / w 3 1 + j w / w 3 1/j w normalizer w 2 / w 3 scaled radial error sledge error signal zero on defect or drop out w 1 w 4 g 67 86 satellite inputs 87 r1 r2 ra radial actuator g e table 13: radial pid parameters [1] parameter controlled by comment w 1 - radial integrator bandwidth w 2 - beginning of radial lead w 3 rad_parm_play end of radial lead (differentiating part) w 4 rad_pole_noise low-pass function following pid w 3 / w 2 rad_length_lead lead length (proportional part) w 5 = ( w 1 . w 2 / w 3 ) rad_int_strength integrator strength g rad_gain radial loop gain g e end stage gain de?ned as peak-to-peak voltage swing over radial actuator 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 53 of 74 philips semiconductors SAA7803 one chip cd audio device 6.7.5.2 level initialization during start-up an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for tpi level generation. the initialization procedure runs in a radial open loop situation and is 300 ms. this start-up time period may coincide with the last part of the motor start-up time period: ? automatic gain adjustment: as a result of this initialization the amplitude of the re signal is adjusted to within 10 % around the nominal re amplitude ? offset adjustment: the additional offset in re due to the limited accuracy of the start-up procedure is less than 50 nm ? tpi level generation: the accuracy of the initialization procedure is such that the duty factor range of tpi becomes 0.4 < duty factor < 0.6 (default duty factor = tpi high/tpi period). 6.7.5.3 sledge control the microprocessor can move the sledge in both directions via the steer sledge command. 6.7.5.4 tracking control the actuator is controlled using a pid loop ?lter with user de?ned coef?cients and gain. for stable operation between the tracks, the s-curve is extended over 0.75 of the track. on request from the microprocessor, s-curve extension over 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks. both modes of s-curve extension use a track-count mechanism. in this mode, track counting results in an automatic return-to-zero track to avoid major disturbances in the audio output and providing improved shock resistance. the sledge is continuously controlled, or provided with step pulses to reduce power consumption using the ?ltered value of the radial pid output. alternatively, the microprocessor can read the average voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. filter coef?cients of the continuous sledge control can be preset by the user. fig 33. bode diagram of radial pid system frequency (log hz) rad_lead_length rad_pole_lead rad_pole_noise 001aab776 rad_int rad_int_strength i w 5 w 1 w 2 w 3 w 4 p d amplitude (db) rad_gain 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 54 of 74 philips semiconductors SAA7803 one chip cd audio device 6.7.5.5 access the access procedure is divided into two different modes (see t ab le 14 ), depending on the requested jump size. [1] microprocessor presettable. the access procedure makes use of a track counting mechanism, a velocity signal based on a ?xed number of tracks passed within a ?xed time interval, a velocity set point calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. if the number of tracks remaining is greater than the brake_distance then the sledge jump mode should be activated or, the actuator jump should be performed. the requested jump size together with the required sledge breaking distance at maximum access speed de?nes the brake_distance value. during the actuator jump mode, velocity control with a pi controller is used for the actuator. the sledge is then continuously controlled using the ?ltered value of the radial pid output. all ?lter parameters (for actuator and sledge) are user programmable. in the sledge jump mode, maximum power (user programmable) is applied to the sledge in the correct direction while the actuator becomes idle (the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated). the actuator can be electronically damped during sledge jump. the gain of the damping loop is controlled via the hold_mult parameter. the fast track jumping circuitry can be enabled or disabled via the xtra_preset parameter. 6.7.5.6 radial automatic gain control loop the loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. this gain control injects a signal into the loop which is used to correct the loop gain. since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). this gain control differs from the level initialization. the level initialization should be performed ?rst. the disadvantage of using the level initialization without the gain control is that only tolerances from the front-end are reduced. 6.7.6 off-track counting the track position indicator (tpi) is a ?ag which is used to indicate whether the radial spot is positioned on the track, with a margin of 1 4 of the track-pitch. in combination with the radial polarity ?ag (rp) the relative spot position over the tracks can be determined. these signals can have uncertainties caused by: ? disc defects such as scratches and ?ngerprints ? the hf information on the disc, which is considered as noise by the detector signals. table 14: access types access type jump size access speed actuator jump brake_distance [1] decreasing velocity sledge jump brake_distance - 32768 maximum power to sledge 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 55 of 74 philips semiconductors SAA7803 one chip cd audio device in order to determine the spot position with suf?cient accuracy, extra conditions are necessary to generate a track loss signal (tl) and an off-track counter value. these extra conditions in?uence the maximum speed and this implies that, internally, one of the following three counting states is selected: ? protected state; used in normal play situations; a good protection against false detection caused by disc defects is important in this state ? slow counting state; used in low velocity track jump situations; in this state a fast response is important rather than the protection against disc defects (if the phase relationship between tl and rp of 1 2 p radians is affected too much, then the direction cannot be determined accurately) ? fast counting state; used in high velocity track jump situations; highest obtainable velocity is the most important feature in this state. 6.7.7 defect detection a defect detection circuit is incorporated into the SAA7803. if a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. the defect detector can be switched off, applied only to focus control or applied to both focus and radial controls under software control (part of foc_parm1). the defect detector has programmable set points selectable by the parameter defect_parm. 6.7.8 off-track detection during active radial tracking, off-track detection has been released by continuously monitoring the off-track counter value. the off-track ?ag becomes valid whenever the off-track counter value is not equal to zero. depending on the type of extended s-curve, the off-track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode. 6.7.9 high level features 6.7.9.1 automatic error handling three watchdogs are present: ? focus: detects focus dropout of longer than 3 ms, sets focus lost interrupt, switches off radial and sledge servos, disables drive to disc motor ? radial play: started when radial servo is in on-track mode and a ?rst subcode frame is found; detects when maximum time between two subcode frames exceeds the time set by playwatchtime parameter; then sets radial error interrupt, switches radial and sledge servos off, puts disc motor in jump mode fig 34. defect detector diagram decimation filter fast filter defect generation programmable hold-off slow filter defect output r1 r2 86 87 + - 001aab777 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 56 of 74 philips semiconductors SAA7803 one chip cd audio device ? radial jump: active when radial servo is in long jump or short jump modes; detects when the off-track counter value decreases by less than 4 tracks between two readings (time interval set by jumpwatchtime parameter); then sets radial jump error, switches radial and sledge servos off to cancel jump. the focus watchdog is always active, the radial watchdogs are selectable via the radcontrol parameter. 6.7.9.2 automatic sequencers and timer interrupts two automatic sequencers are implemented (and must be initialized after power-on): ? autostart sequencer: controls the start-up of focus, radial and motor ? autostop sequencer: brakes the disc and shuts down servos. when the automatic sequencers are not used it is possible to generate timer interrupts, de?ned by the time_parameter coef?cient. 6.7.10 driver interface the control signals (pins ra, fo and sl) for the mechanism actuators are pulse density modulated. the modulating frequency can be set to either 1.0584 mhz or 2.1168 mhz; controlled via the xtra_preset parameter. an analog representation of the output signals can be achieved by connecting a ?rst-order low-pass ?lter to the outputs. during reset (i.e. pin reset_n is held low) the ra, fo, and sl pins are high-impedance. at all other times, when the laser is switched off, the ra and fo pins output a 2 mhz, 50 % duty cycle signal. 6.8 laser interface the laser diode pre-amp function is built onto the SAA7803 and is illustrated in figure 35 . the current can be regulated, up to 120 ma, in four steps ranging from 58 % up to full power. the voltage derived from the monitor diode is maintained at a steady state by the laser drive circuitry, regulating the current through the laser diode. fig 35. laser control circuit 001aab779 up/down counter 78 77 76 monitor laser_ion laser power vmon_dac laser_comp_out laser_pdmin laser_clk8mhz laser lpower timing and control logic sigma delta dac dac laser diode and monitor laser_clk32mhz 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 57 of 74 philips semiconductors SAA7803 one chip cd audio device 6.9 arm7 system the following diagram identi?es the component parts which make up the system. the following sections give you a top-level description of the individual blocks. 6.9.1 arm7tdmi-s? microprocessor the arm7tdmi-s processor is a member of the arm family of 32-bit microprocessors. the arm processor offers a high performance for low power consumption and low gate count. the arm architecture is based upon reduced instruction set computer (risc) principles. risc provides the following key bene?ts: ? high instruction throughput ? excellent real time interrupt response. [1] the frequency of operation will depend on the performance required for the SAA7803 application and the software complexity. the arm7tdmi-s processor has 2 instruction sets: ? the 32-bit arm instruction set ? the 16-bit arm thumb instruction. the arm uses a 3 stage pipeline to increase the throughput of the ?ow of instructions to the processor. this allows several operations to operate simultaneously and the processor and memory systems to operate continuously. fig 36. top level arm hierarchy 001aab780 arm7tdmi-s static memory interface unit laser driver channel decoder interface 32 kb rom interface 4 kb ram interface ahb vpb bridge pdsic core lcd driver audio dac headphone volume controller i 2 s-bus i 2 c-bus uart vpb bus ahb bus interrupt controller gpio table 15: performance characteristics for arm7tdmi-s process technology ( m m) performance (mips/mhz) power consumption (mw/mhz) maximum operating frequency (mhz) typical operating frequency requirements for SAA7803 0.18 0.9 0.39 67 2 mhz [1] 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 58 of 74 philips semiconductors SAA7803 one chip cd audio device the 3 stage pipelines can be de?ned in the following stages: ? fetch cycle; this is used to fetch the instruction from the memory ? decode cycle; this is used to decode the registers, used in the instructions fetched ? execute cycle; this is used to fetch the data from register banks, the shift and alu operations are performed and the data is written back into the memory. the microprocessors have traditionally the same width for the instructions and data. the 32-bit architecture can be more ef?cient in performance and could also address a much larger address space compared to 16-bit architectures. the code density for 16-bit architecture would be much higher than 32-bit and the performance would be greater than half the 32-bit performance. the arm thumb instructions concept addresses the issues when 16-bit instructions are used but the performance required is for 32-bit architecture. therefore the aim of thumb instruction set can be summarized as follows: ? higher performance for 16-bit architecture if 16-bit instructions are to be used. ? the code density achieved for 16-bit instructions in a 32-bit architecture is a much more ef?cient usage of memory space. 6.9.2 static memory interface unit (smiu) the ahb sram controller implements an ahb slave interface to an external sram. this interface is only available in the development version of this device. the speci?cation of this interface is: ? 32-bit ahb interface width ? 67 mhz maximum ahb operating frequency ? con?gured for low latency ? 1 kb memory word depth ? 32-bit data. 6.9.3 rom interface the rom interface provides an interface between the onboard 4 kb srom memory and the arm via the ahb bus. the speci?cation of this interface is: ? 32-bit ahb interface width ? 67 mhz maximum ahb operating frequency ? con?gured for low latency ? 8 kb memory word depth ? 32-bit data. the low latency architecture is optimized for low speed operation. no wait states are used and the rom control signals are taken directly from the ahb bus. this means that the maximum frequency is likely to be limited by the speed at which the control signals arrive from the ahb master 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 59 of 74 philips semiconductors SAA7803 one chip cd audio device 6.9.4 ram interface the ram interface provides an interface between the onboard 32 kb sram memory and the arm via the ahb bus. the speci?cation of this interface is: ? 32-bit ahb interface width ? 67 mhz maximum ahb operating frequency ? con?gured for low latency ? 1 kb memory word depth ? 32-bit data. 6.9.5 i 2 c-bus interface this interface can be used as an i 2 c-bus slave or master and is fully compliant with the i 2 c-bus speci?cation. the speci?cation of this interface is: ? master/slave con?gurations ? address 30h ? 67 mhz maximum ahb operating frequency ? 25 mhz i 2 c-bus operating frequency ? 4 byte rx fifo depth ? 4 byte tx fifo depth ? maximum i 2 c-bus frequency of 400 khz ? compatible with 7-bit and 10-bit addressing. 6.9.6 general purpose i/os the gpios are linked to the vlsi peripheral bus (vpb). this interface provides individual control over each bidirectional pin. each pin can be con?gured to be an input, output or bidirectional: ? 32 bidirectional i/os. 6.9.7 interrupt controller ? 12 dedicated internal interrupts ? 1 external interrupt which has programmable polarity ? two interrupt types available interrupt request (irq) and fast interrupt request (fiq) ? interrupts can be de?ned as irq or fiq ? one of 16 priority levels can be assigned to an interrupt ? interrupt priority threshold level ? all interrupts can be masked. 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 60 of 74 philips semiconductors SAA7803 one chip cd audio device 6.9.8 universal asynchronous receiver transceiver ? 4 byte tx fifo depth ? 4 byte rx fifo depth ? both rx and tx can have speci?c ?ll levels set before an interrupt is triggered ? format of data character to be transmitted or received can be de?ned. 7. code development the SAA7803 is the ?rmware development platform for the saa7804 and saa7806 devices. figure 37 indicates the concept behind the mcm architecture. further detail is given in the following sections. 7.1 memory the development memories are organized differently from the saa7804 and saa7806 arm rom, the address range is identical i.e. 8 kb locations but the development memories are 16 bits wide rather than the 32-bit width of the arm rom. the smiu compensates for this variation in location widths, avoiding the need for different address ranges between the software for the mask programmable arm rom and the development software. pin int_ex_rom is used to select between the onboard arm rom memory and the mcms external memories. fig 37. multichip module concept 001aab782 jtag serial to parallel flash rom 0.25 mbit sram 0.25 mbit arm rom ahb interface arm smiu tck SAA7803 trst_n tms tdi int_ex_rom 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 61 of 74 philips semiconductors SAA7803 one chip cd audio device 7.2 transfer and execution of code code is transferred to the development memory via a jtag interface using the protocol speci?ed in the ieee1149.1 standard. a detailed description of the download and transfer stages is not given since customer software has been developed to facilitate this task. two types of external memory are used in the mcm. development code is initially streamed to the ?ash rom and then transferred to the sram from where it is executed. code is executed from the sram to take advantage of its superior access times. 7.3 operating speeds code execution using development memory is slower than execution from the mask programmed rom. the reasons for this are: ? the smiu interface to development memory requires additional clock cycles to fetch instructions ? development memory locations are only 16 bits wide whereas masked programmed rom locations are 32 bits wide. 8. limiting values [1] all digital input and bidirectional pins are 5 v tolerant [2] maximum absolute voltage at receiver inputs during transient conditions. transient voltage time durations are limited to t settle,cm (10 ms maximum). table 16: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ddd digital supply voltage - 0.5 +2.5 v v ddp periphery supply voltage - 0.5 +3.6 v v dda analog supply voltage - 0.5 +3.6 v v lcd analog lcd supply voltage - 0.5 +5.5 v v i input voltage analog inputs - 0.5 v dda + 0.5 v 5 v tolerant digital inputs [1] - 0.5 5.5 v receiver input transient [2] - 0.5 v t stg storage temperature - 55 +125 c p tot total power dissipation playing disc at 1 with headphones enabled - 274 mw 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 62 of 74 philips semiconductors SAA7803 one chip cd audio device 9. recommended operating conditions 10. characteristics table 17: recommended operating conditions symbol parameter conditions min typ max unit v ddd digital supply voltage 1.65 1.80 1.95 v v ddp pad supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.0 3.3 3.6 v v lcd analog lcd supply voltage 4.5 5.0 5.5 v t amb ambient temperature - 25 - c table 18: characteristics v ddp = v dda = 3.0 v to 3.6 v; v ddd = 1.65 v to 1.95 v; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v ddd supply voltage, digital regulator 1.65 1.8 1.95 v v ddp supply voltage, digital pads 3.0 3.3 3.6 v v dda supply voltage, analog 3.0 3.3 3.6 v i ddd supply current, digital v ddd = 1.8 v [1] 9.6 15.5 42.4 ma i dda supply current, analog v dda = 3.3 v [2] [3] 63.6 63.6 63.6 ma i ddp supply current, peripheral v ddp = 3.3 v [2] [4] 11.1 11.1 11.1 ma voltage regulator v ddd supply voltage, digital core 1.65 1.8 1.95 v v ddd(tx) supply voltage, analog transmitter 1.65 1.8 1.95 v v ddd(rx) supply voltage, analog receiver 1.65 1.8 1.95 v analog section (v dda = 3.3 v; v ssa = 0) lf path; input pins r1 and r2 d v i(p) peak signal amplitude voltage range (16 steps) unidirectional 20 - 960 mv bidirectional 20 - 960 mv ? g tol ? gain tolerance absolute - 20 - +20 % d g tol(ch) relative gain tolerance between channels within a pair - 3 0 +3 % d v offset(dc) dc offset cancellation range relative to full-scale unidirectional - 66 - % bidirectional - 33 - % d g t cancellation accuracy relative to full-scale - 4.1 - % f s sample frequency - 4.2336 - mhz f i input frequency (2f s ) - 8.4672 - mhz b recovered bandwidth 20 - - khz s/n signal to noise ratio 0 khz to 20 khz 55 - - db thd total harmonic distortion 0 khz to 20 khz - - - 30 db r i(v) input resistance in voltage mode b = 0 khz to 20 khz 20 - - k w 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 63 of 74 philips semiconductors SAA7803 one chip cd audio device r i(v)(tol) voltage mode resistance tolerance - 30 - +30 % v cm(min) minimum input common mode range - 1.6 - v v io input offset relative to pin opu_ref_out - 30 - +30 mv hf path; input pins d1, d2, d3 and d4 v i(adc) 6-bit adc input range peak-to-peak differential 1.4 1.4 1.4 v v cm(adc) 6-bit adc common mode voltage 2 --v b bandwidth up to 6 (2 mhz x x-rate) 12 - - mhz t d( j )(f) phase delay ?atness up to 6 (10ns/x-rate) - - 1.66 ns s/n signal to noise ratio 100 hz to 12 mhz - - 28 db v o(p-p) output swing (peak-to-peak value) at 6 mhz - - 1 v d distortion at 6 mhz - - - 35 db psrr power supply rejection 40 - - db d g total gain range 2.4 - 38.4 db z i input impedance nominal 20 20 20 k w b mon hf monitor bandwidth - 3 db point 27 - 46 mhz audio dac; input/output pin dac_vref; output pins dac_ln, dac_lp, dac_rn and dac_rp s/n aw a-weighted signal-to-noise ratio - 90 - db thd total harmonic distortion at 1 khz - - - 80 db audio feature; input pins aux_l and aux_r s/n signal to noise ratio 0 khz to 20 khz 55 - - db thd total harmonic distortion 0 khz to 20 khz - - - 30 db headphone buffer; input pins aux_l and aux_r; output pins buf_out_l and buf_out_r g gain - 39 - +6 db s/n aw a-weighted signal-to-noise ratio 90 - - db thd dac total harmonic distortion (dac input) at 1 khz - - - 80 db thd aux total harmonic distortion (aux input) at 1 khz - - - 80 db v o/p(p-p) o/p voltage swing (peak-to-peak value) - 2.2 - v z i input impedance 32 - - k w laser driver; input pin monitor l (o)max output current 120 - - ma t su time for laser to reach ?nal value 1 - - ms v window voltage excursion (noise) - 1 - +1 mv table 18: characteristics continued v ddp = v dda = 3.0 v to 3.6 v; v ddd = 1.65 v to 1.95 v; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 64 of 74 philips semiconductors SAA7803 one chip cd audio device v o output voltage sel180 = 0 145 - 155 mv sel180 = 1 175 - 185 mv output pin: opu_ref_out v i(ref) band gap reference voltage - 1.6 - v oscillator input pin oscin (external clock) v i input voltage - v dda /2 - v t h input high time relative to period 45 - 55 % i li input leakage current - 20 - +20 ma c i input capacitance - - 7 pf output pin: oscout f oscout oscillator frequency crystal [5] 8.4672 - 16.9344 mhz resonator 8.4672 - 16.9344 mhz g m mutual conductance at start-up 17 - - ms c f feedback capacitance - - 2 pf c o output capacitance - - 7 pf r bias internal bias resistor - 200 - k w pinning characteristics general i oz 3-state output leakage current v o = 0 v or v o = v dde --1 m a i lu i/o latch-up current - 0.5 v ddp < v < 1.5 v ddp ; t j < 125 c 100 - - ma v esd human body model - - kv machine model - - v power i max maximum continuous current - - 98 ma digital pins dc speci?cations input and bi-directional pins v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i il low-level input current v i = 0 v; no pull up - - 1 m a i ih high-level input current v i = v ddp --1 m a parameter for pin types with hysteresis (pin types idh and iuh) v hys hysteresis voltage 0.4 - - v parameter for pin types with pull-down (types id and idh) i pd pull-down current v i = v ddp 20 50 75 ma v i = 5 v 20 50 75 ma table 18: characteristics continued v ddp = v dda = 3.0 v to 3.6 v; v ddd = 1.65 v to 1.95 v; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 65 of 74 philips semiconductors SAA7803 one chip cd audio device [1] v ddd1 and v ddd2 . [2] minimum value is initial reset value; primary clock = 67 mhz; ahb and decoder = 4 mhz. typical and maximum value with playing cd at 1 ; headphone buffer enabled; primary clock = 67 mhz. for typical value ahb = 16 mhz and decoder = 4 mhz; for maximum value, ahb = 67 mhz and decoder = 4 mhz. [3] v dda1 , v dda2 , v dda3 and v dd(dac) . [4] v ddp1 , v ddp2 and v ddp3 . [5] it is recommended that the nominal running series resistance of the crystal or ceramic resonator is 60 w . parameter for pin types with pull-up (types btsu, iu and iuh) i pu pull-up current v i = 0 v - 13 - 50 - 40 ma v ddp < v i < 5.0 v 0 0 0 ma dc speci?cations output and bi-directional pins v oh high-level output voltage v ddp - 0.4 - - v v ol low-level output voltage - - 0.4 v i ol low-level output current v ol = 0.4 v 5 ns slew rate output 4 - - ma 12 ma output 11 - - ma 27 ma output 27 - - ma i oh high-level output current v oh = v ddp - 0.4 v 5 ns slew rate output - 5 --ma 12 ma output - 13--ma 27 ma output - 28--ma i oh(sc) high-level short-circuit current short period of time; v oh =0v -- - 45 ma i ol(sc) low-level short-circuit current short period of time; v ol =v ddp - - 50 ma ac speci?cations input pins t r , t f rise and fall time - 6 200 ns ac speci?cations output and bi-directional pins parameter for pin types with slew rate limited output (types bts, btsu and ots) t thl , t tlh transition times c l = 30 pf; transition times read at 10 % and 90 % of output slope; 5 ns slew rate output - 4.0 - ns parameter for pin types with slew rate limited output and 12 ma source or sink current (type aobs) t thl , t tlh transition times c l = 30 pf; transition times read at 10 % and 90 % of output slope; 5 ns slew rate output; 12 ma output - 2.9 - ns parameter for pin types with 27 ma source or sink current (type os) t thl , t tlh transition times c l = 30 pf; transition times read at 10 % and 90 % of output slope; 27 ma output - 3.8 - ns table 18: characteristics continued v ddp = v dda = 3.0 v to 3.6 v; v ddd = 1.65 v to 1.95 v; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit 4 .com u datasheet
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 66 of 74 philips semiconductors SAA7803 one chip cd audio device 11. application information fig 38. typical application diagram SAA7803 81 123456789101112131415161718192021222324252627282930 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 v dda1 d1 d2 d3 d4 r1 r2 aux_l aux_r v dda2 opu_ref_out v ssa2 oscout oscin v dd(dac) dac_lp dac_ln dac_vref dac_rn dac_rp v ss(dacf) v ss(dacb) buf_out_l buf_out_r v dda3 a_in_1/gpio0 a_in_2/gpio1 tx/gpio_ana rx/gpio_ana sda scl v ssd1 reset_n v dd1 lkill rkill v ssp1 dobm v ddp1 seg0/gpio4 seg1/gpio5 seg2/gpio6 seg3/gpio7 seg4/gpio8 seg5/gpio9 seg6/gpio10 seg7/gpio11 seg8/gpio12 seg9/gpio13 v lcd hf_mon v ssa1 monitor laser lpower tdo2/gpio31 int/gpio30/rtck tms2/gpio29 tdi2/gpio28 v ddd2 v ssd2 sl fo ra moto2 moto1 td0 trst_n tck tms tdi v ddp3 v ssp3 v4/cl16 sync sclk wclk data ef sdi 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 scli sb2 sb1 3.3 v 1.8 v r5 3.3 k w r4 3.3 k w r3 3.3 k w r2 3.3 k w r11 10 k w r12 10 k w mute c2 4.7 nf c1 4.7 nf c1 4.7 nf c5 33 pf c6 33 pf 8.4672 mhz left right dac out g1 c10 4.7 nf c8 10 nf c9 10 nf c7 1 m f r10 2.7 k w c11 4.7 nf c3 4.7 nf c4 6.8 nf jtag port sledge opu connections focus radial spindle 3.3 v wcli v ddp2 int_ex_rom v ssp2 com3/gpio27 com2/gpio26 com1/gpio25 com0/gpio24 seg19/gpio23/gflg seg18/gpio22/meas seg17/gpio21/cl1 001aab783 seg16/gpio20 seg15/gpio19 v dd(led) seg14/gpio18 3.3 v seg13/gpio17 seg12/gpio16 seg11/gpio15 seg10/gpio14 reset 1.8 v r1 10 k w optional tza1048 u2 u1 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc radoutn focoutp gnd focoutn radoutp v cc v cc sloutp sloutn gnd motoutp motoutn v cc vout3.3 vfbin3.3 vout1.8 vfbin1.8 mute radin focin gnd slin vbiasin gnd vbiasout motbias motin1 motin2 spindle r8 1 % 1 % 1 % 1 % 10 k w r9 12 k w r6 3.3 k w r7 3.3 k w sledge focus radial 3.3 v v1 bc337 v2 bc337 1.8 v 3.3 v 8 v tr2 focus radial opu servos sp2 tr1 tr mo sp mo sp1 gnd m 3.3 v pin 81 c13 22 m f (25 v) c14 2.2 nf 3.3 v pin 90 c15 22 m f (25 v) c16 2.2 nf 3.3 v pin 95 c17 22 m f (25 v) c18 2.2 nf 3.3 v pin decoupling pin 5 c19 22 m f (25 v) c20 2.2 nf 3.3 v pin 19 c21 22 m f (25 v) c22 2.2 nf 3.3 v pin 48 c23 22 m f (25 v) c24 2.2 nf 3.3 v pin 59 c25 22 m f (25 v) c26 2.2 nf 3.3 v pin 76 c27 22 m f (25 v) c28 2.2 nf 3.3 v pin 14 c31 22 m f (25 v) c32 2.2 nf 3.3 v pin 71 c33 22 m f (25 v) c34 2.2 nf 3.3 v pin 76 c35 22 m f (25 v) c36 2.2 nf 3.3 v pin 36 c29 100 nf 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 67 of 74 philips semiconductors SAA7803 one chip cd audio device 12. package outline fig 39. package outline sot317-2 (qfp100) unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 14.1 13.9 0.65 18.2 17.6 1.0 0.6 7 0 o o 0.15 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot317-2 mo-112 99-12-27 03-02-25 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 0.8 0.4 d e q e a 1 a l p detail x l (a ) 3 b 30 c b p e h a 2 d z d a z e e v m a 1 100 81 80 51 50 31 pin 1 index x y b p d h v m b w m w m 0 5 10 mm scale qfp100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot317-2 a max. 3.2 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 68 of 74 philips semiconductors SAA7803 one chip cd audio device 13. soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 13.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 69 of 74 philips semiconductors SAA7803 one chip cd audio device C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 13.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 19: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 70 of 74 philips semiconductors SAA7803 one chip cd audio device [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 14. abbreviations table 20: abbreviations acronym description ahb arm advanced high performance bus arm advanced risc machines (32-bit microprocessor design) arm7tdmi-s speci?c version of arm microprocessor used in SAA7803 (arm7 family) fifo first in, first out gpio general purpose input/output hsi hardware software interface speci?cation i 2 c inter ic-bus communication format i 2 s inter ic sound format lcd liquid crystal display mcm multi chip module pdsic parallel digital servo ic (digital servo block within SAA7803) risc reduced instruction set computer thumb arm 16-bit instruction set uart universal asynchronous receiver transmitter vpb vlsi peripheral bus 4 .com u datasheet
9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 71 of 74 philips semiconductors SAA7803 one chip cd audio device 15. revision history table 21: revision history document id release date data sheet status change notice doc. number supersedes SAA7803_1 20050419 objective data sheet - 9397 750 13695 - 4 .com u datasheet
philips semiconductors SAA7803 one chip cd audio device 9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 72 of 74 16. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 18. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 19. trademarks thumb is a registered trademark of arm limited. arm is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. 20. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 4 .com u datasheet
philips semiconductors SAA7803 one chip cd audio device 9397 750 13695 ? koninklijke philips electronics n.v. 2005. all rights reserved. objective data sheet rev. 01 19 april 2005 73 of 74 continued >> 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 hardware features . . . . . . . . . . . . . . . . . . . . . . 1 2.2 read formats . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 8 6.1 analog data acquisition. . . . . . . . . . . . . . . . . . . 8 6.1.1 lf acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1.2 hf acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 analog clock generation . . . . . . . . . . . . . . . . . 10 6.3 general purpose analog inputs . . . . . . . . . . . 11 6.4 auxiliary analog inputs . . . . . . . . . . . . . . . . . . 11 6.5 ahb core clock generation . . . . . . . . . . . . . . . 13 6.6 channel decoder . . . . . . . . . . . . . . . . . . . . . . 14 6.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.6.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.3 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.6.3.1 signal xclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.6.3.2 sysclock domain. . . . . . . . . . . . . . . . . . . . . . . 18 6.6.3.3 bit clock domain . . . . . . . . . . . . . . . . . . . . . . . 18 6.6.3.4 ebu clock domain . . . . . . . . . . . . . . . . . . . . . 18 6.6.4 decoder to arm microprocessor interface . . . 19 6.6.4.1 programming interface . . . . . . . . . . . . . . . . . . 19 6.6.4.2 interrupt strategy. . . . . . . . . . . . . . . . . . . . . . . 19 6.6.5 efm bit detection and demodulation . . . . . . . 19 6.6.5.1 signal conditioning . . . . . . . . . . . . . . . . . . . . . 20 6.6.5.2 bit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.6.5.3 limiting the pll frequency range . . . . . . . . . . 29 6.6.5.4 run length 2 pushback detector . . . . . . . . . . . 30 6.6.5.5 available signals for monitoring . . . . . . . . . . . 30 6.6.5.6 format of the measurement signal on meas pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.6.5.7 demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.6.5.8 efm demodulation . . . . . . . . . . . . . . . . . . . . . 32 6.6.5.9 sync detection and synchronization . . . . . . . . 32 6.6.5.10 sync protection . . . . . . . . . . . . . . . . . . . . . . . . 32 6.6.6 cd decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.6.6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.6.6.2 q-channel subcode interface . . . . . . . . . . . . . 33 6.6.6.3 cd-text interface . . . . . . . . . . . . . . . . . . . . . 34 6.6.6.4 main data decoding . . . . . . . . . . . . . . . . . . . . 35 6.6.6.5 error corrector statistics . . . . . . . . . . . . . . . . . 37 6.6.7 audio back-end and data output interfaces . . 37 6.6.7.1 audio processing . . . . . . . . . . . . . . . . . . . . . . 38 6.6.7.2 interpolate and hold . . . . . . . . . . . . . . . . . . . . 38 6.6.7.3 soft mute and error detection. . . . . . . . . . . . . 39 6.6.7.4 hard mute on ebu . . . . . . . . . . . . . . . . . . . . . 39 6.6.7.5 silence detection and kill generation . . . . . . . 39 6.6.7.6 de-emphasis ?lter . . . . . . . . . . . . . . . . . . . . . 40 6.6.7.7 upsample ?lter (four times) . . . . . . . . . . . . . . 40 6.6.7.8 data output interfaces . . . . . . . . . . . . . . . . . . 41 6.6.7.9 i 2 s-bus interface. . . . . . . . . . . . . . . . . . . . . . . 41 6.6.7.10 ebu interface . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.6.7.11 subcode interface . . . . . . . . . . . . . . . . . . . . . 43 6.6.8 motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6.8.1 frequency set point . . . . . . . . . . . . . . . . . . . . 44 6.6.8.2 position error . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.6.8.3 motor control loop gains (k p , k f and k i ). . . . . 45 6.6.8.4 operation modes . . . . . . . . . . . . . . . . . . . . . . 45 6.6.8.5 writing and reading motor integrator value . . 46 6.6.8.6 some notes on application motor servo. . . . . 46 6.7 digital servo - pdsic. . . . . . . . . . . . . . . . . . . 46 6.7.1 pdsic registers and servo ram control . . . 46 6.7.2 diode signal processing . . . . . . . . . . . . . . . . . 48 6.7.3 signal conditioning . . . . . . . . . . . . . . . . . . . . . 48 6.7.4 focus servo system . . . . . . . . . . . . . . . . . . . . 50 6.7.4.1 focus start-up . . . . . . . . . . . . . . . . . . . . . . . . 50 6.7.4.2 focus position control loop. . . . . . . . . . . . . . . 50 6.7.4.3 dropout detection. . . . . . . . . . . . . . . . . . . . . . 51 6.7.4.4 focus loss detection and fast restart . . . . . . . 51 6.7.4.5 focus loop gain switching . . . . . . . . . . . . . . . 51 6.7.4.6 focus automatic gain control loop . . . . . . . . . 52 6.7.5 radial servo system. . . . . . . . . . . . . . . . . . . . 52 6.7.5.1 radial pid - on-track mode . . . . . . . . . . . . . . 52 6.7.5.2 level initialization . . . . . . . . . . . . . . . . . . . . . . 53 6.7.5.3 sledge control . . . . . . . . . . . . . . . . . . . . . . . . 53 6.7.5.4 tracking control . . . . . . . . . . . . . . . . . . . . . . . 53 6.7.5.5 access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7.5.6 radial automatic gain control loop . . . . . . . . . 54 6.7.6 off-track counting . . . . . . . . . . . . . . . . . . . . . . 54 6.7.7 defect detection . . . . . . . . . . . . . . . . . . . . . . . 55 6.7.8 off-track detection . . . . . . . . . . . . . . . . . . . . . 55 6.7.9 high level features . . . . . . . . . . . . . . . . . . . . . 55 6.7.9.1 automatic error handling . . . . . . . . . . . . . . . . 55 6.7.9.2 automatic sequencers and timer interrupts . . 56 6.7.10 driver interface . . . . . . . . . . . . . . . . . . . . . . . . 56 6.8 laser interface . . . . . . . . . . . . . . . . . . . . . . . . 56 6.9 arm7 system. . . . . . . . . . . . . . . . . . . . . . . . . 57 6.9.1 arm7tdmi-s? microprocessor . . . . . . . . . . 57 6.9.2 static memory interface unit (smiu) . . . . . . . 58 6.9.3 rom interface . . . . . . . . . . . . . . . . . . . . . . . . 58 4 .com u datasheet
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 19 april 2005 document number: 9397 750 13695 published in the netherlands philips semiconductors SAA7803 one chip cd audio device 6.9.4 ram interface . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.9.5 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 59 6.9.6 general purpose i/os . . . . . . . . . . . . . . . . . . . 59 6.9.7 interrupt controller . . . . . . . . . . . . . . . . . . . . . 59 6.9.8 universal asynchronous receiver transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7 code development. . . . . . . . . . . . . . . . . . . . . . 60 7.1 memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.2 transfer and execution of code . . . . . . . . . . . . 61 7.3 operating speeds . . . . . . . . . . . . . . . . . . . . . . 61 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 61 9 recommended operating conditions. . . . . . . 62 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 62 11 application information. . . . . . . . . . . . . . . . . . 66 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 67 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 68 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 68 13.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 69 13.5 package related soldering information . . . . . . 69 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 70 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 71 16 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 72 17 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 19 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 20 contact information . . . . . . . . . . . . . . . . . . . . 72 4 .com u datasheet

▲Up To Search▲

Price & Availability of SAA7803

	To Download SAA7803 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .